1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 22 23 struct mxc_ccm_reg { 24 u32 ccr; /* 0x0000 */ 25 u32 ccdr; 26 u32 csr; 27 u32 ccsr; 28 u32 cacrr; /* 0x0010*/ 29 u32 cbcdr; 30 u32 cbcmr; 31 u32 cscmr1; 32 u32 cscmr2; /* 0x0020 */ 33 u32 cscdr1; 34 u32 cs1cdr; 35 u32 cs2cdr; 36 u32 cdcdr; /* 0x0030 */ 37 u32 chsccdr; 38 u32 cscdr2; 39 u32 cscdr3; 40 u32 cscdr4; /* 0x0040 */ 41 u32 resv0; 42 u32 cdhipr; 43 u32 cdcr; 44 u32 ctor; /* 0x0050 */ 45 u32 clpcr; 46 u32 cisr; 47 u32 cimr; 48 u32 ccosr; /* 0x0060 */ 49 u32 cgpr; 50 u32 CCGR0; 51 u32 CCGR1; 52 u32 CCGR2; /* 0x0070 */ 53 u32 CCGR3; 54 u32 CCGR4; 55 u32 CCGR5; 56 u32 CCGR6; /* 0x0080 */ 57 u32 CCGR7; 58 u32 cmeor; 59 u32 resv[0xfdd]; 60 u32 analog_pll_sys; /* 0x4000 */ 61 u32 analog_pll_sys_set; 62 u32 analog_pll_sys_clr; 63 u32 analog_pll_sys_tog; 64 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 65 u32 analog_usb1_pll_480_ctrl_set; 66 u32 analog_usb1_pll_480_ctrl_clr; 67 u32 analog_usb1_pll_480_ctrl_tog; 68 u32 analog_reserved0[4]; 69 u32 analog_pll_528; /* 0x4030 */ 70 u32 analog_pll_528_set; 71 u32 analog_pll_528_clr; 72 u32 analog_pll_528_tog; 73 u32 analog_pll_528_ss; /* 0x4040 */ 74 u32 analog_reserved1[3]; 75 u32 analog_pll_528_num; /* 0x4050 */ 76 u32 analog_reserved2[3]; 77 u32 analog_pll_528_denom; /* 0x4060 */ 78 u32 analog_reserved3[3]; 79 u32 analog_pll_audio; /* 0x4070 */ 80 u32 analog_pll_audio_set; 81 u32 analog_pll_audio_clr; 82 u32 analog_pll_audio_tog; 83 u32 analog_pll_audio_num; /* 0x4080*/ 84 u32 analog_reserved4[3]; 85 u32 analog_pll_audio_denom; /* 0x4090 */ 86 u32 analog_reserved5[3]; 87 u32 analog_pll_video; /* 0x40a0 */ 88 u32 analog_pll_video_set; 89 u32 analog_pll_video_clr; 90 u32 analog_pll_video_tog; 91 u32 analog_pll_video_num; /* 0x40b0 */ 92 u32 analog_reserved6[3]; 93 u32 analog_pll_vedio_denon; /* 0x40c0 */ 94 u32 analog_reserved7[7]; 95 u32 analog_pll_enet; /* 0x40e0 */ 96 u32 analog_pll_enet_set; 97 u32 analog_pll_enet_clr; 98 u32 analog_pll_enet_tog; 99 u32 analog_pfd_480; /* 0x40f0 */ 100 u32 analog_pfd_480_set; 101 u32 analog_pfd_480_clr; 102 u32 analog_pfd_480_tog; 103 u32 analog_pfd_528; /* 0x4100 */ 104 u32 analog_pfd_528_set; 105 u32 analog_pfd_528_clr; 106 u32 analog_pfd_528_tog; 107 }; 108 109 /* Define the bits in register CCR */ 110 #define MXC_CCM_CCR_RBC_EN (1 << 27) 111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 115 #define MXC_CCM_CCR_COSC_EN (1 << 12) 116 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 117 #define MXC_CCM_CCR_OSCNT_OFFSET 0 118 119 /* Define the bits in register CCDR */ 120 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 121 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 122 123 /* Define the bits in register CSR */ 124 #define MXC_CCM_CSR_COSC_READY (1 << 5) 125 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 126 127 /* Define the bits in register CCSR */ 128 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 129 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 130 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 131 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 132 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 133 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 134 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 135 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 136 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 137 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 138 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 139 140 /* Define the bits in register CACRR */ 141 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 142 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 143 144 /* Define the bits in register CBCDR */ 145 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 146 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 147 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) 148 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 149 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 150 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 151 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 152 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 153 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 154 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 155 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 156 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 157 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 158 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 159 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 160 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 161 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 162 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 163 164 /* Define the bits in register CBCMR */ 165 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 166 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 167 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 168 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 169 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 170 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 171 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 172 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 173 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) 174 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 175 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 176 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 177 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 178 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 179 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 180 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 181 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 182 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 183 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 184 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 185 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 186 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 187 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 188 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) 189 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) 190 191 /* Define the bits in register CSCMR1 */ 192 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 193 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 194 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 195 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 196 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 197 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 198 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 199 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 200 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 201 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 202 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 203 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 204 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 205 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 206 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 207 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 208 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 209 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 210 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 211 212 /* Define the bits in register CSCMR2 */ 213 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 214 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 215 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 216 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 217 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) 218 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 219 220 /* Define the bits in register CSCDR1 */ 221 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 222 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 223 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 224 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 225 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 226 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 227 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 228 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 229 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 230 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 231 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 232 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 233 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 234 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 235 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 236 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 237 238 /* Define the bits in register CS1CDR */ 239 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 240 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 241 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 242 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 243 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 244 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 245 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 246 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 247 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 248 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 249 250 /* Define the bits in register CS2CDR */ 251 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 252 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 253 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 254 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 255 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) 256 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 257 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 258 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 259 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 260 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 261 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 262 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 263 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 264 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 265 266 /* Define the bits in register CDCDR */ 267 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 268 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 269 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 270 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 271 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 272 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) 273 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 274 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 275 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 276 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 277 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 278 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 279 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 280 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 281 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 282 283 /* Define the bits in register CHSCCDR */ 284 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 285 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 286 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 287 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 288 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 289 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 290 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 291 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 292 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 293 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 294 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 295 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 296 297 #define CHSCCDR_CLK_SEL_LDB_DI0 3 298 #define CHSCCDR_PODF_DIVIDE_BY_3 2 299 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 300 301 /* Define the bits in register CSCDR2 */ 302 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 303 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 304 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 305 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 306 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 307 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 308 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 309 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 310 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 311 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 312 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 313 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 314 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 315 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 316 317 /* Define the bits in register CSCDR3 */ 318 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 319 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 320 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 321 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 322 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 323 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 324 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 325 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 326 327 /* Define the bits in register CDHIPR */ 328 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 329 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 330 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 331 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 332 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 333 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 334 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 335 336 /* Define the bits in register CLPCR */ 337 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 338 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 339 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 340 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 341 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 342 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 343 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 344 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 345 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 346 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) 347 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 348 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 349 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 350 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 351 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 352 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 353 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 354 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 355 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 356 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 357 #define MXC_CCM_CLPCR_LPM_MASK 0x3 358 #define MXC_CCM_CLPCR_LPM_OFFSET 0 359 360 /* Define the bits in register CISR */ 361 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 362 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 363 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 364 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 365 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 366 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 367 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 368 #define MXC_CCM_CISR_COSC_READY (1 << 6) 369 #define MXC_CCM_CISR_LRF_PLL 1 370 371 /* Define the bits in register CIMR */ 372 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 373 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 374 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 375 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 376 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 377 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) 378 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 379 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 380 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 381 382 /* Define the bits in register CCOSR */ 383 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 384 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 385 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 386 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 387 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 388 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 389 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 390 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 391 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 392 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 393 394 /* Define the bits in registers CGPR */ 395 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 396 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 397 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 398 399 /* Define the bits in registers CCGRx */ 400 #define MXC_CCM_CCGR_CG_MASK 3 401 402 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 403 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 404 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 405 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 406 #define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4 407 #define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA) 408 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 409 #define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET) 410 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 411 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 412 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 413 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 414 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 415 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 416 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 417 #define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET) 418 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 419 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 420 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 421 #define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET) 422 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 423 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 424 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 425 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 426 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 427 #define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET) 428 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 429 #define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET) 430 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 431 #define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET) 432 433 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 434 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET) 435 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 436 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET) 437 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 438 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET) 439 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 440 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET) 441 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 442 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET) 443 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 444 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) 445 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 446 #define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET) 447 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 448 #define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET) 449 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 450 #define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET) 451 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 452 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET) 453 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 454 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 455 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 456 #define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET) 457 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 458 #define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET) 459 460 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 461 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 462 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 463 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 464 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 465 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 466 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 467 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 468 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 469 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 470 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 471 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 472 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 473 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 474 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 475 #define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET) 476 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 477 #define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET) 478 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 479 #define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET) 480 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 481 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 482 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 483 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 484 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 485 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 486 487 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 488 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 489 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 490 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 491 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 492 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 493 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 494 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 495 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 496 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 497 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 498 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 499 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 500 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET) 501 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 502 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET) 503 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 504 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 505 #define MXC_CCM_CCGR3_MLB_OFFSET 18 506 #define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET) 507 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 508 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 509 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 510 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 511 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 512 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 513 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 514 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 515 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 516 #define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET) 517 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 518 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 519 520 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 521 #define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET) 522 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 523 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 524 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 525 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 526 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 527 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 528 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 529 #define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET) 530 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 531 #define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET) 532 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 533 #define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET) 534 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 535 #define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET) 536 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 537 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 538 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 539 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 540 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 541 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 542 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 543 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 544 545 #define MXC_CCM_CCGR5_ROM_OFFSET 0 546 #define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET) 547 #define MXC_CCM_CCGR5_SATA_OFFSET 4 548 #define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET) 549 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 550 #define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET) 551 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 552 #define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET) 553 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 554 #define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET) 555 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 556 #define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET) 557 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 558 #define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET) 559 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 560 #define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET) 561 #define MXC_CCM_CCGR5_UART_OFFSET 24 562 #define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET) 563 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 564 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 565 566 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 567 #define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET) 568 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 569 #define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET) 570 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 571 #define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET) 572 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 573 #define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET) 574 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 575 #define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET) 576 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 577 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 578 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 579 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 580 581 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 582 #define BP_ANADIG_PLL_SYS_RSVD0 20 583 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 584 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 585 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 586 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 587 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 588 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 589 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 590 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 591 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 592 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 593 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 594 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 595 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 596 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 597 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 598 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 599 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 600 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 601 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 602 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 603 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 604 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 605 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 606 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 607 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 608 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 609 610 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 611 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 612 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 613 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 614 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 615 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 616 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 617 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 618 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 619 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 620 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 621 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 622 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 623 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 624 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 625 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 626 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 627 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 628 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 629 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 630 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 631 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 632 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 633 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 634 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 635 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 636 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 637 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 638 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 639 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 640 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 641 642 #define BM_ANADIG_PLL_528_LOCK 0x80000000 643 #define BP_ANADIG_PLL_528_RSVD1 19 644 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 645 #define BF_ANADIG_PLL_528_RSVD1(v) \ 646 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 647 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 648 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 649 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 650 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 651 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 652 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 653 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 654 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 655 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 656 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 657 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 658 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 659 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 660 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 661 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 662 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 663 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 664 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 665 #define BP_ANADIG_PLL_528_RSVD0 1 666 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 667 #define BF_ANADIG_PLL_528_RSVD0(v) \ 668 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 669 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 670 671 #define BP_ANADIG_PLL_528_SS_STOP 16 672 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 673 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 674 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 675 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 676 #define BP_ANADIG_PLL_528_SS_STEP 0 677 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 678 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 679 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 680 681 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 682 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 683 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 684 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 685 #define BP_ANADIG_PLL_528_NUM_A 0 686 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 687 #define BF_ANADIG_PLL_528_NUM_A(v) \ 688 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 689 690 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 691 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 692 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 693 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 694 #define BP_ANADIG_PLL_528_DENOM_B 0 695 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 696 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 697 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 698 699 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 700 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 701 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 702 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 703 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 704 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 705 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 706 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 707 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 708 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 709 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 710 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 711 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 712 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 713 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 714 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 715 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 716 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 717 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 718 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 719 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 720 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 721 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 722 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 723 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 724 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 725 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 726 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 727 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 728 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 729 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 730 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 731 732 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 733 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 734 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 735 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 736 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 737 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 738 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 739 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 740 741 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 742 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 743 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 744 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 745 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 746 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 747 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 748 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 749 750 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 751 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 752 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 753 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 754 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 755 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 756 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 757 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 758 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ 759 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) 760 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 761 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 762 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 763 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 764 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 765 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 766 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 767 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 768 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 769 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 770 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 771 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 772 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 773 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 774 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 775 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 776 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 777 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 778 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 779 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 780 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 781 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 782 783 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 784 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 785 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 786 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 787 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 788 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 789 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 790 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 791 792 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 793 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 794 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 795 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 796 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 797 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 798 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 799 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 800 801 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 802 #define BP_ANADIG_PLL_ENET_RSVD1 21 803 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 804 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 805 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 806 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 807 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 808 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 809 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 810 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 811 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 812 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 813 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 814 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 815 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 816 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 817 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 818 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 819 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 820 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 821 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 822 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 823 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 824 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 825 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 826 #define BP_ANADIG_PLL_ENET_RSVD0 2 827 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 828 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 829 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 830 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 831 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 832 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 833 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 834 835 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 836 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 837 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 838 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 839 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 840 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 841 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 842 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 843 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 844 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 845 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 846 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 847 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 848 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 849 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 850 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 851 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 852 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 853 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 854 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 855 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 856 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 857 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 858 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 859 860 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 861 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 862 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 863 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 864 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 865 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 866 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 867 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 868 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 869 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 870 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 871 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 872 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 873 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 874 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 875 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 876 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 877 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 878 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 879 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 880 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 881 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 882 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 883 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 884 885 #define PLL2_PFD0_FREQ 352000000 886 #define PLL2_PFD1_FREQ 594000000 887 #define PLL2_PFD2_FREQ 400000000 888 #define PLL2_PFD2_DIV_FREQ 200000000 889 #define PLL3_PFD0_FREQ 720000000 890 #define PLL3_PFD1_FREQ 540000000 891 #define PLL3_PFD2_FREQ 508200000 892 #define PLL3_PFD3_FREQ 454700000 893 #define PLL3_80M 80000000 894 #define PLL3_60M 60000000 895 896 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 897