1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 22 23 struct mxc_ccm_reg { 24 u32 ccr; /* 0x0000 */ 25 u32 ccdr; 26 u32 csr; 27 u32 ccsr; 28 u32 cacrr; /* 0x0010*/ 29 u32 cbcdr; 30 u32 cbcmr; 31 u32 cscmr1; 32 u32 cscmr2; /* 0x0020 */ 33 u32 cscdr1; 34 u32 cs1cdr; 35 u32 cs2cdr; 36 u32 cdcdr; /* 0x0030 */ 37 u32 chscdr; 38 u32 cscdr2; 39 u32 cscdr3; 40 u32 cscdr4; /* 0x0040 */ 41 u32 resv0; 42 u32 cdhipr; 43 u32 cdcr; 44 u32 ctor; /* 0x0050 */ 45 u32 clpcr; 46 u32 cisr; 47 u32 cimr; 48 u32 ccosr; /* 0x0060 */ 49 u32 cgpr; 50 u32 CCGR0; 51 u32 CCGR1; 52 u32 CCGR2; /* 0x0070 */ 53 u32 CCGR3; 54 u32 CCGR4; 55 u32 CCGR5; 56 u32 CCGR6; /* 0x0080 */ 57 u32 CCGR7; 58 u32 cmeor; 59 u32 resv[0xfdd]; 60 u32 analog_pll_sys; /* 0x4000 */ 61 u32 analog_pll_sys_set; 62 u32 analog_pll_sys_clr; 63 u32 analog_pll_sys_tog; 64 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 65 u32 analog_usb1_pll_480_ctrl_set; 66 u32 analog_usb1_pll_480_ctrl_clr; 67 u32 analog_usb1_pll_480_ctrl_tog; 68 u32 analog_reserved0[4]; 69 u32 analog_pll_528; /* 0x4030 */ 70 u32 analog_pll_528_set; 71 u32 analog_pll_528_clr; 72 u32 analog_pll_528_tog; 73 u32 analog_pll_528_ss; /* 0x4040 */ 74 u32 analog_reserved1[3]; 75 u32 analog_pll_528_num; /* 0x4050 */ 76 u32 analog_reserved2[3]; 77 u32 analog_pll_528_denom; /* 0x4060 */ 78 u32 analog_reserved3[3]; 79 u32 analog_pll_audio; /* 0x4070 */ 80 u32 analog_pll_audio_set; 81 u32 analog_pll_audio_clr; 82 u32 analog_pll_audio_tog; 83 u32 analog_pll_audio_num; /* 0x4080*/ 84 u32 analog_reserved4[3]; 85 u32 analog_pll_audio_denom; /* 0x4090 */ 86 u32 analog_reserved5[3]; 87 u32 analog_pll_video; /* 0x40a0 */ 88 u32 analog_pll_video_set; 89 u32 analog_pll_video_clr; 90 u32 analog_pll_video_tog; 91 u32 analog_pll_video_num; /* 0x40b0 */ 92 u32 analog_reserved6[3]; 93 u32 analog_pll_vedio_denon; /* 0x40c0 */ 94 u32 analog_reserved7[7]; 95 u32 analog_pll_enet; /* 0x40e0 */ 96 u32 analog_pll_enet_set; 97 u32 analog_pll_enet_clr; 98 u32 analog_pll_enet_tog; 99 u32 analog_pfd_480; /* 0x40f0 */ 100 u32 analog_pfd_480_set; 101 u32 analog_pfd_480_clr; 102 u32 analog_pfd_480_tog; 103 u32 analog_pfd_528; /* 0x4100 */ 104 u32 analog_pfd_528_set; 105 u32 analog_pfd_528_clr; 106 u32 analog_pfd_528_tog; 107 }; 108 109 /* Define the bits in register CCR */ 110 #define MXC_CCM_CCR_RBC_EN (1 << 27) 111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 115 #define MXC_CCM_CCR_COSC_EN (1 << 12) 116 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 117 #define MXC_CCM_CCR_OSCNT_OFFSET 0 118 119 /* Define the bits in register CCDR */ 120 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 121 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 122 123 /* Define the bits in register CSR */ 124 #define MXC_CCM_CSR_COSC_READY (1 << 5) 125 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 126 127 /* Define the bits in register CCSR */ 128 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 129 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 130 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 131 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 132 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 133 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 134 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 135 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 136 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 137 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 138 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 139 140 /* Define the bits in register CACRR */ 141 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 142 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 143 144 /* Define the bits in register CBCDR */ 145 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 146 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 147 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) 148 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 149 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 150 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 151 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 152 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 153 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 154 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 155 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 156 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 157 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 158 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 159 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 160 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 161 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 162 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 163 164 /* Define the bits in register CBCMR */ 165 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 166 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 167 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 168 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 169 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 170 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 171 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 172 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 173 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) 174 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 175 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 176 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 177 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 178 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 179 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 180 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 181 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 182 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 183 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 184 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 185 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 186 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 187 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 188 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) 189 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) 190 191 /* Define the bits in register CSCMR1 */ 192 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 193 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 194 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 195 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 196 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 197 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 198 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 199 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 200 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 201 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 202 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 203 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 204 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 205 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 206 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 207 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 208 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 209 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 210 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 211 212 /* Define the bits in register CSCMR2 */ 213 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 214 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 215 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 216 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 217 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) 218 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 219 220 /* Define the bits in register CSCDR1 */ 221 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 222 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 223 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 224 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 225 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 226 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 227 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 228 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 229 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 230 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 231 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 232 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 233 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 234 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 235 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 236 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 237 238 /* Define the bits in register CS1CDR */ 239 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 240 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 241 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 242 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 243 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 244 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 245 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 246 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 247 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 248 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 249 250 /* Define the bits in register CS2CDR */ 251 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 252 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 253 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 254 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 255 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) 256 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 257 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 258 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 259 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 260 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 261 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 262 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 263 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 264 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 265 266 /* Define the bits in register CDCDR */ 267 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 268 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 269 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 270 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 271 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 272 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) 273 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 274 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 275 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 276 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 277 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 278 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 279 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 280 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 281 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 282 283 /* Define the bits in register CHSCCDR */ 284 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 285 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 286 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 287 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 288 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 289 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 290 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 291 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 292 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 293 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 294 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 295 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 296 297 /* Define the bits in register CSCDR2 */ 298 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 299 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 300 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 301 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 302 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 303 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 304 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 305 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 306 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 307 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 308 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 309 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 310 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 311 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 312 313 /* Define the bits in register CSCDR3 */ 314 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 315 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 316 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 317 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 318 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 319 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 320 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 321 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 322 323 /* Define the bits in register CDHIPR */ 324 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 325 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 326 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 327 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 328 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 329 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 330 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 331 332 /* Define the bits in register CLPCR */ 333 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 334 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 335 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 336 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 337 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 338 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 339 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 340 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 341 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 342 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) 343 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 344 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 345 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 346 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 347 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 348 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 349 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 350 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 351 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 352 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 353 #define MXC_CCM_CLPCR_LPM_MASK 0x3 354 #define MXC_CCM_CLPCR_LPM_OFFSET 0 355 356 /* Define the bits in register CISR */ 357 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 358 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 359 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 360 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 361 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 362 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 363 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 364 #define MXC_CCM_CISR_COSC_READY (1 << 6) 365 #define MXC_CCM_CISR_LRF_PLL 1 366 367 /* Define the bits in register CIMR */ 368 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 369 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 370 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 371 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 372 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 373 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) 374 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 375 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 376 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 377 378 /* Define the bits in register CCOSR */ 379 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 380 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 381 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 382 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 383 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 384 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 385 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 386 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 387 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 388 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 389 390 /* Define the bits in registers CGPR */ 391 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 392 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 393 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 394 395 /* Define the bits in registers CCGRx */ 396 #define MXC_CCM_CCGR_CG_MASK 3 397 398 #define MXC_CCM_CCGR0_CG15_OFFSET 30 399 #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30) 400 #define MXC_CCM_CCGR0_CG14_OFFSET 28 401 #define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28) 402 #define MXC_CCM_CCGR0_CG13_OFFSET 26 403 #define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26) 404 #define MXC_CCM_CCGR0_CG12_OFFSET 24 405 #define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24) 406 #define MXC_CCM_CCGR0_CG11_OFFSET 22 407 #define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22) 408 #define MXC_CCM_CCGR0_CG10_OFFSET 20 409 #define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20) 410 #define MXC_CCM_CCGR0_CG9_OFFSET 18 411 #define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18) 412 #define MXC_CCM_CCGR0_CG8_OFFSET 16 413 #define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16) 414 #define MXC_CCM_CCGR0_CG7_OFFSET 14 415 #define MXC_CCM_CCGR0_CG6_OFFSET 12 416 #define MXC_CCM_CCGR0_CG5_OFFSET 10 417 #define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10) 418 #define MXC_CCM_CCGR0_CG4_OFFSET 8 419 #define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8) 420 #define MXC_CCM_CCGR0_CG3_OFFSET 6 421 #define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6) 422 #define MXC_CCM_CCGR0_CG2_OFFSET 4 423 #define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4) 424 #define MXC_CCM_CCGR0_CG1_OFFSET 2 425 #define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2) 426 #define MXC_CCM_CCGR0_CG0_OFFSET 0 427 #define MXC_CCM_CCGR0_CG0_MASK 3 428 429 #define MXC_CCM_CCGR1_CG15_OFFSET 30 430 #define MXC_CCM_CCGR1_CG14_OFFSET 28 431 #define MXC_CCM_CCGR1_CG13_OFFSET 26 432 #define MXC_CCM_CCGR1_CG12_OFFSET 24 433 #define MXC_CCM_CCGR1_CG11_OFFSET 22 434 #define MXC_CCM_CCGR1_CG10_OFFSET 20 435 #define MXC_CCM_CCGR1_CG9_OFFSET 18 436 #define MXC_CCM_CCGR1_CG8_OFFSET 16 437 #define MXC_CCM_CCGR1_CG7_OFFSET 14 438 #define MXC_CCM_CCGR1_CG6_OFFSET 12 439 #define MXC_CCM_CCGR1_CG5_OFFSET 10 440 #define MXC_CCM_CCGR1_CG4_OFFSET 8 441 #define MXC_CCM_CCGR1_CG3_OFFSET 6 442 #define MXC_CCM_CCGR1_CG2_OFFSET 4 443 #define MXC_CCM_CCGR1_CG1_OFFSET 2 444 #define MXC_CCM_CCGR1_CG0_OFFSET 0 445 446 #define MXC_CCM_CCGR2_CG15_OFFSET 30 447 #define MXC_CCM_CCGR2_CG14_OFFSET 28 448 #define MXC_CCM_CCGR2_CG13_OFFSET 26 449 #define MXC_CCM_CCGR2_CG12_OFFSET 24 450 #define MXC_CCM_CCGR2_CG11_OFFSET 22 451 #define MXC_CCM_CCGR2_CG10_OFFSET 20 452 #define MXC_CCM_CCGR2_CG9_OFFSET 18 453 #define MXC_CCM_CCGR2_CG8_OFFSET 16 454 #define MXC_CCM_CCGR2_CG7_OFFSET 14 455 #define MXC_CCM_CCGR2_CG6_OFFSET 12 456 #define MXC_CCM_CCGR2_CG5_OFFSET 10 457 #define MXC_CCM_CCGR2_CG4_OFFSET 8 458 #define MXC_CCM_CCGR2_CG3_OFFSET 6 459 #define MXC_CCM_CCGR2_CG2_OFFSET 4 460 #define MXC_CCM_CCGR2_CG1_OFFSET 2 461 #define MXC_CCM_CCGR2_CG0_OFFSET 0 462 463 #define MXC_CCM_CCGR3_CG15_OFFSET 30 464 #define MXC_CCM_CCGR3_CG14_OFFSET 28 465 #define MXC_CCM_CCGR3_CG13_OFFSET 26 466 #define MXC_CCM_CCGR3_CG12_OFFSET 24 467 #define MXC_CCM_CCGR3_CG11_OFFSET 22 468 #define MXC_CCM_CCGR3_CG10_OFFSET 20 469 #define MXC_CCM_CCGR3_CG9_OFFSET 18 470 #define MXC_CCM_CCGR3_CG8_OFFSET 16 471 #define MXC_CCM_CCGR3_CG7_OFFSET 14 472 #define MXC_CCM_CCGR3_CG6_OFFSET 12 473 #define MXC_CCM_CCGR3_CG5_OFFSET 10 474 #define MXC_CCM_CCGR3_CG4_OFFSET 8 475 #define MXC_CCM_CCGR3_CG3_OFFSET 6 476 #define MXC_CCM_CCGR3_CG2_OFFSET 4 477 #define MXC_CCM_CCGR3_CG1_OFFSET 2 478 #define MXC_CCM_CCGR3_CG0_OFFSET 0 479 480 #define MXC_CCM_CCGR4_CG15_OFFSET 30 481 #define MXC_CCM_CCGR4_CG14_OFFSET 28 482 #define MXC_CCM_CCGR4_CG13_OFFSET 26 483 #define MXC_CCM_CCGR4_CG12_OFFSET 24 484 #define MXC_CCM_CCGR4_CG11_OFFSET 22 485 #define MXC_CCM_CCGR4_CG10_OFFSET 20 486 #define MXC_CCM_CCGR4_CG9_OFFSET 18 487 #define MXC_CCM_CCGR4_CG8_OFFSET 16 488 #define MXC_CCM_CCGR4_CG7_OFFSET 14 489 #define MXC_CCM_CCGR4_CG6_OFFSET 12 490 #define MXC_CCM_CCGR4_CG5_OFFSET 10 491 #define MXC_CCM_CCGR4_CG4_OFFSET 8 492 #define MXC_CCM_CCGR4_CG3_OFFSET 6 493 #define MXC_CCM_CCGR4_CG2_OFFSET 4 494 #define MXC_CCM_CCGR4_CG1_OFFSET 2 495 #define MXC_CCM_CCGR4_CG0_OFFSET 0 496 497 #define MXC_CCM_CCGR5_CG15_OFFSET 30 498 #define MXC_CCM_CCGR5_CG14_OFFSET 28 499 #define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28) 500 #define MXC_CCM_CCGR5_CG13_OFFSET 26 501 #define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26) 502 #define MXC_CCM_CCGR5_CG12_OFFSET 24 503 #define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24) 504 #define MXC_CCM_CCGR5_CG11_OFFSET 22 505 #define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22) 506 #define MXC_CCM_CCGR5_CG10_OFFSET 20 507 #define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20) 508 #define MXC_CCM_CCGR5_CG9_OFFSET 18 509 #define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18) 510 #define MXC_CCM_CCGR5_CG8_OFFSET 16 511 #define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16) 512 #define MXC_CCM_CCGR5_CG7_OFFSET 14 513 #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) 514 #define MXC_CCM_CCGR5_CG6_OFFSET 12 515 #define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) 516 #define MXC_CCM_CCGR5_CG5_OFFSET 10 517 #define MXC_CCM_CCGR5_CG4_OFFSET 8 518 #define MXC_CCM_CCGR5_CG3_OFFSET 6 519 #define MXC_CCM_CCGR5_CG2_OFFSET 4 520 #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) 521 #define MXC_CCM_CCGR5_CG1_OFFSET 2 522 #define MXC_CCM_CCGR5_CG0_OFFSET 0 523 524 #define MXC_CCM_CCGR6_CG15_OFFSET 30 525 #define MXC_CCM_CCGR6_CG14_OFFSET 28 526 #define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) 527 #define MXC_CCM_CCGR6_CG13_OFFSET 26 528 #define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) 529 #define MXC_CCM_CCGR6_CG12_OFFSET 24 530 #define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) 531 #define MXC_CCM_CCGR6_CG11_OFFSET 22 532 #define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) 533 #define MXC_CCM_CCGR6_CG10_OFFSET 20 534 #define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) 535 #define MXC_CCM_CCGR6_CG9_OFFSET 18 536 #define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) 537 #define MXC_CCM_CCGR6_CG8_OFFSET 16 538 #define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) 539 #define MXC_CCM_CCGR6_CG7_OFFSET 14 540 #define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) 541 #define MXC_CCM_CCGR6_CG6_OFFSET 12 542 #define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12) 543 #define MXC_CCM_CCGR6_CG5_OFFSET 10 544 #define MXC_CCM_CCGR6_CG4_OFFSET 8 545 #define MXC_CCM_CCGR6_CG3_OFFSET 6 546 #define MXC_CCM_CCGR6_CG2_OFFSET 4 547 #define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) 548 #define MXC_CCM_CCGR6_CG1_OFFSET 2 549 #define MXC_CCM_CCGR6_CG0_OFFSET 0 550 551 #define MXC_CCM_CCGR7_CG15_OFFSET 30 552 #define MXC_CCM_CCGR7_CG14_OFFSET 28 553 #define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) 554 #define MXC_CCM_CCGR7_CG13_OFFSET 26 555 #define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) 556 #define MXC_CCM_CCGR7_CG12_OFFSET 24 557 #define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) 558 #define MXC_CCM_CCGR7_CG11_OFFSET 22 559 #define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) 560 #define MXC_CCM_CCGR7_CG10_OFFSET 20 561 #define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) 562 #define MXC_CCM_CCGR7_CG9_OFFSET 18 563 #define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) 564 #define MXC_CCM_CCGR7_CG8_OFFSET 16 565 #define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) 566 #define MXC_CCM_CCGR7_CG7_OFFSET 14 567 #define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) 568 #define MXC_CCM_CCGR7_CG6_OFFSET 12 569 #define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) 570 #define MXC_CCM_CCGR7_CG5_OFFSET 10 571 #define MXC_CCM_CCGR7_CG4_OFFSET 8 572 #define MXC_CCM_CCGR7_CG3_OFFSET 6 573 #define MXC_CCM_CCGR7_CG2_OFFSET 4 574 #define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) 575 #define MXC_CCM_CCGR7_CG1_OFFSET 2 576 #define MXC_CCM_CCGR7_CG0_OFFSET 0 577 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 578 #define BP_ANADIG_PLL_SYS_RSVD0 20 579 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 580 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 581 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 582 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 583 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 584 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 585 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 586 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 587 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 588 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 589 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 590 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 591 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 592 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 593 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 594 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 595 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 596 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 597 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 598 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 599 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 600 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 601 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 602 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 603 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 604 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 605 606 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 607 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 608 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 609 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 610 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 611 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 612 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 613 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 614 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 615 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 616 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 617 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 618 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 619 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 620 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 621 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 622 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 623 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 624 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 625 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 626 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 627 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 628 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 629 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 630 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 631 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 632 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 633 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 634 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 635 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 636 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 637 638 #define BM_ANADIG_PLL_528_LOCK 0x80000000 639 #define BP_ANADIG_PLL_528_RSVD1 19 640 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 641 #define BF_ANADIG_PLL_528_RSVD1(v) \ 642 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 643 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 644 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 645 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 646 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 647 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 648 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 649 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 650 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 651 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 652 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 653 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 654 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 655 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 656 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 657 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 658 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 659 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 660 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 661 #define BP_ANADIG_PLL_528_RSVD0 1 662 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 663 #define BF_ANADIG_PLL_528_RSVD0(v) \ 664 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 665 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 666 667 #define BP_ANADIG_PLL_528_SS_STOP 16 668 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 669 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 670 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 671 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 672 #define BP_ANADIG_PLL_528_SS_STEP 0 673 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 674 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 675 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 676 677 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 678 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 679 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 680 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 681 #define BP_ANADIG_PLL_528_NUM_A 0 682 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 683 #define BF_ANADIG_PLL_528_NUM_A(v) \ 684 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 685 686 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 687 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 688 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 689 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 690 #define BP_ANADIG_PLL_528_DENOM_B 0 691 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 692 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 693 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 694 695 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 696 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 697 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 698 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 699 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 700 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 701 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 702 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 703 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 704 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 705 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 706 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 707 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 708 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 709 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 710 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 711 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 712 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 713 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 714 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 715 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 716 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 717 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 718 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 719 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 720 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 721 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 722 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 723 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 724 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 725 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 726 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 727 728 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 729 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 730 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 731 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 732 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 733 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 734 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 735 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 736 737 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 738 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 739 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 740 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 741 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 742 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 743 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 744 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 745 746 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 747 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 748 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 749 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 750 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 751 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 752 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 753 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 754 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ 755 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) 756 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 757 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 758 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 759 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 760 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 761 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 762 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 763 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 764 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 765 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 766 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 767 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 768 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 769 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 770 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 771 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 772 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 773 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 774 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 775 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 776 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 777 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 778 779 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 780 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 781 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 782 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 783 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 784 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 785 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 786 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 787 788 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 789 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 790 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 791 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 792 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 793 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 794 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 795 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 796 797 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 798 #define BP_ANADIG_PLL_ENET_RSVD1 21 799 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 800 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 801 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 802 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 803 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 804 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 805 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 806 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 807 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 808 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 809 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 810 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 811 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 812 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 813 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 814 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 815 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 816 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 817 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 818 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 819 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 820 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 821 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 822 #define BP_ANADIG_PLL_ENET_RSVD0 2 823 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 824 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 825 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 826 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 827 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 828 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 829 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 830 831 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 832 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 833 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 834 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 835 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 836 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 837 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 838 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 839 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 840 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 841 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 842 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 843 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 844 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 845 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 846 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 847 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 848 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 849 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 850 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 851 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 852 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 853 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 854 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 855 856 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 857 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 858 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 859 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 860 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 861 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 862 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 863 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 864 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 865 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 866 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 867 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 868 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 869 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 870 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 871 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 872 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 873 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 874 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 875 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 876 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 877 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 878 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 879 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 880 881 #define PLL2_PFD0_FREQ 352000000 882 #define PLL2_PFD1_FREQ 594000000 883 #define PLL2_PFD2_FREQ 400000000 884 #define PLL2_PFD2_DIV_FREQ 200000000 885 #define PLL3_PFD0_FREQ 720000000 886 #define PLL3_PFD1_FREQ 540000000 887 #define PLL3_PFD2_FREQ 508200000 888 #define PLL3_PFD3_FREQ 454700000 889 #define PLL3_80M 80000000 890 #define PLL3_60M 60000000 891 892 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 893