1 /*
2  * (C) Copyright 2009
3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __ASM_ARCH_CLOCK_H
9 #define __ASM_ARCH_CLOCK_H
10 
11 #include <common.h>
12 
13 #ifdef CONFIG_SYS_MX6_HCLK
14 #define MXC_HCLK	CONFIG_SYS_MX6_HCLK
15 #else
16 #define MXC_HCLK	24000000
17 #endif
18 
19 #ifdef CONFIG_SYS_MX6_CLK32
20 #define MXC_CLK32	CONFIG_SYS_MX6_CLK32
21 #else
22 #define MXC_CLK32	32768
23 #endif
24 
25 enum mxc_clock {
26 	MXC_ARM_CLK = 0,
27 	MXC_PER_CLK,
28 	MXC_AHB_CLK,
29 	MXC_IPG_CLK,
30 	MXC_IPG_PERCLK,
31 	MXC_UART_CLK,
32 	MXC_CSPI_CLK,
33 	MXC_AXI_CLK,
34 	MXC_EMI_SLOW_CLK,
35 	MXC_DDR_CLK,
36 	MXC_ESDHC_CLK,
37 	MXC_ESDHC2_CLK,
38 	MXC_ESDHC3_CLK,
39 	MXC_ESDHC4_CLK,
40 	MXC_SATA_CLK,
41 	MXC_NFC_CLK,
42 	MXC_I2C_CLK,
43 };
44 
45 enum enet_freq {
46 	ENET_25MHZ,
47 	ENET_50MHZ,
48 	ENET_100MHZ,
49 	ENET_125MHZ,
50 };
51 
52 u32 imx_get_uartclk(void);
53 u32 imx_get_fecclk(void);
54 unsigned int mxc_get_clock(enum mxc_clock clk);
55 void setup_gpmi_io_clk(u32 cfg);
56 void hab_caam_clock_enable(unsigned char enable);
57 void enable_ocotp_clk(unsigned char enable);
58 void enable_usboh3_clk(unsigned char enable);
59 void enable_uart_clk(unsigned char enable);
60 int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
61 int enable_sata_clock(void);
62 void disable_sata_clock(void);
63 int enable_pcie_clock(void);
64 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
65 int enable_spi_clk(unsigned char enable, unsigned spi_num);
66 void enable_ipu_clock(void);
67 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
68 void enable_enet_clk(unsigned char enable);
69 int enable_lcdif_clock(u32 base_addr);
70 void enable_qspi_clk(int qspi_num);
71 void enable_thermal_clk(void);
72 void mxs_set_lcdclk(u32 base_addr, u32 freq);
73 #endif /* __ASM_ARCH_CLOCK_H */
74