1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
25 
26 #if defined(CONFIG_MX51)
27 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
28 #define IPU_CTRL_BASE_ADDR	0x40000000
29 #define SPBA0_BASE_ADDR         0x70000000
30 #define AIPS1_BASE_ADDR         0x73F00000
31 #define AIPS2_BASE_ADDR         0x83F00000
32 #define CSD0_BASE_ADDR          0x90000000
33 #define CSD1_BASE_ADDR          0xA0000000
34 #define NFC_BASE_ADDR_AXI       0xCFFF0000
35 #define CS1_BASE_ADDR           0xB8000000
36 #elif defined(CONFIG_MX53)
37 #define IPU_CTRL_BASE_ADDR      0x18000000
38 #define SPBA0_BASE_ADDR         0x50000000
39 #define AIPS1_BASE_ADDR         0x53F00000
40 #define AIPS2_BASE_ADDR         0x63F00000
41 #define CSD0_BASE_ADDR          0x70000000
42 #define CSD1_BASE_ADDR          0xB0000000
43 #define NFC_BASE_ADDR_AXI       0xF7FF0000
44 #define IRAM_BASE_ADDR          0xF8000000
45 #define CS1_BASE_ADDR           0xF4000000
46 #define SATA_BASE_ADDR		0x10000000
47 #else
48 #error "CPU_TYPE not defined"
49 #endif
50 
51 #define IRAM_SIZE		0x00020000	/* 128 KB */
52 
53 /*
54  * SPBA global module enabled #0
55  */
56 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
57 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
58 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
59 #define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
60 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
61 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
62 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
63 #define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
64 #define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
65 #define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
66 #define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
67 #define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
68 
69 /*
70  * AIPS 1
71  */
72 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
73 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
74 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
75 #define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
76 #define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
77 #define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
78 #define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
79 #define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
80 #define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
81 #define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
82 #define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
83 #define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
84 #define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
85 #define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
86 #define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
87 #define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
88 #define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
89 #define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
90 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
91 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
92 
93 #if defined(CONFIG_MX53)
94 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
95 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
96 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
97 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
98 #endif
99 /*
100  * AIPS 2
101  */
102 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
103 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
104 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
105 #ifdef	CONFIG_MX53
106 #define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
107 #endif
108 #define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
109 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
110 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
111 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
112 #define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
113 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
114 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
115 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
116 #define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
117 #define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
118 #define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
119 #define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
120 #define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
121 #define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
122 #define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
123 #define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
124 #define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
125 #define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
126 #define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
127 #define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
128 #define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
129 #define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
130 #define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
131 #define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
132 #define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
133 #define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
134 #define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
135 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
136 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
137 
138 #if defined(CONFIG_MX53)
139 #define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
140 #endif
141 
142 /*
143  * WEIM CSnGCR1
144  */
145 #define CSEN		1
146 #define SWR		(1 << 1)
147 #define SRD		(1 << 2)
148 #define MUM		(1 << 3)
149 #define WFL		(1 << 4)
150 #define RFL		(1 << 5)
151 #define CRE		(1 << 6)
152 #define CREP		(1 << 7)
153 #define BL(x)		(((x) & 0x7) << 8)
154 #define WC		(1 << 11)
155 #define BCD(x)		(((x) & 0x3) << 12)
156 #define BCS(x)		(((x) & 0x3) << 14)
157 #define DSZ(x)		(((x) & 0x7) << 16)
158 #define SP		(1 << 19)
159 #define CSREC(x)	(((x) & 0x7) << 20)
160 #define AUS		(1 << 23)
161 #define GBC(x)		(((x) & 0x7) << 24)
162 #define WP		(1 << 27)
163 #define PSZ(x)		(((x) & 0x0f << 28)
164 
165 /*
166  * WEIM CSnGCR2
167  */
168 #define ADH(x)		(((x) & 0x3))
169 #define DAPS(x)		(((x) & 0x0f << 4)
170 #define DAE		(1 << 8)
171 #define DAP		(1 << 9)
172 #define MUX16_BYP	(1 << 12)
173 
174 /*
175  * WEIM CSnRCR1
176  */
177 #define RCSN(x)		(((x) & 0x7))
178 #define RCSA(x)		(((x) & 0x7) << 4)
179 #define OEN(x)		(((x) & 0x7) << 8)
180 #define OEA(x)		(((x) & 0x7) << 12)
181 #define RADVN(x)	(((x) & 0x7) << 16)
182 #define RAL		(1 << 19)
183 #define RADVA(x)	(((x) & 0x7) << 20)
184 #define RWSC(x)		(((x) & 0x3f) << 24)
185 
186 /*
187  * WEIM CSnRCR2
188  */
189 #define RBEN(x)		(((x) & 0x7))
190 #define RBE		(1 << 3)
191 #define RBEA(x)		(((x) & 0x7) << 4)
192 #define RL(x)		(((x) & 0x3) << 8)
193 #define PAT(x)		(((x) & 0x7) << 12)
194 #define APR		(1 << 15)
195 
196 /*
197  * WEIM CSnWCR1
198  */
199 #define WCSN(x)		(((x) & 0x7))
200 #define WCSA(x)		(((x) & 0x7) << 3)
201 #define WEN(x)		(((x) & 0x7) << 6)
202 #define WEA(x)		(((x) & 0x7) << 9)
203 #define WBEN(x)		(((x) & 0x7) << 12)
204 #define WBEA(x)		(((x) & 0x7) << 15)
205 #define WADVN(x)	(((x) & 0x7) << 18)
206 #define WADVA(x)	(((x) & 0x7) << 21)
207 #define WWSC(x)		(((x) & 0x3f) << 24)
208 #define WBED1		(1 << 30)
209 #define WAL		(1 << 31)
210 
211 /*
212  * WEIM CSnWCR2
213  */
214 #define WBED		1
215 
216 /*
217  * WEIM WCR
218  */
219 #define BCM		1
220 #define GBCD(x)		(((x) & 0x3) << 1)
221 #define INTEN		(1 << 4)
222 #define INTPOL		(1 << 5)
223 #define WDOG_EN		(1 << 8)
224 #define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
225 
226 #define CS0_128					0
227 #define CS0_64M_CS1_64M				1
228 #define CS0_64M_CS1_32M_CS2_32M			2
229 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
230 
231 /*
232  * CSPI register definitions
233  */
234 #define MXC_ECSPI
235 #define MXC_CSPICTRL_EN		(1 << 0)
236 #define MXC_CSPICTRL_MODE	(1 << 1)
237 #define MXC_CSPICTRL_XCH	(1 << 2)
238 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
239 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
240 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
241 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
242 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
243 #define MXC_CSPICTRL_MAXBITS	0xfff
244 #define MXC_CSPICTRL_TC		(1 << 7)
245 #define MXC_CSPICTRL_RXOVF	(1 << 6)
246 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
247 #define MAX_SPI_BYTES	32
248 
249 /* Bit position inside CTRL register to be associated with SS */
250 #define MXC_CSPICTRL_CHAN	18
251 
252 /* Bit position inside CON register to be associated with SS */
253 #define MXC_CSPICON_POL		4
254 #define MXC_CSPICON_PHA		0
255 #define MXC_CSPICON_SSPOL	12
256 #define MXC_SPI_BASE_ADDRESSES \
257 	CSPI1_BASE_ADDR, \
258 	CSPI2_BASE_ADDR, \
259 	CSPI3_BASE_ADDR,
260 
261 /*
262  * Number of GPIO pins per port
263  */
264 #define GPIO_NUM_PIN            32
265 
266 #define IIM_SREV	0x24
267 #define ROM_SI_REV	0x48
268 
269 #define NFC_BUF_SIZE	0x1000
270 
271 /* M4IF */
272 #define M4IF_FBPM0	0x40
273 #define M4IF_FIDBP	0x48
274 
275 /* Assuming 24MHz input clock with doubler ON */
276 /*                            MFI         PDF */
277 #define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
278 #define DP_MFD_864	(180 - 1) /* PL Dither mode */
279 #define DP_MFN_864	180
280 #define DP_MFN_800_DIT	60 /* PL Dither mode */
281 
282 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
283 #define DP_MFD_850	(48 - 1)
284 #define DP_MFN_850	41
285 
286 #define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
287 #define DP_MFD_800	(3 - 1)
288 #define DP_MFN_800	1
289 
290 #define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
291 #define DP_MFD_700	(24 - 1)
292 #define DP_MFN_700	7
293 
294 #define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
295 #define DP_MFD_665	(96 - 1)
296 #define DP_MFN_665	89
297 
298 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
299 #define DP_MFD_532	(24 - 1)
300 #define DP_MFN_532	13
301 
302 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
303 #define DP_MFD_400	(3 - 1)
304 #define DP_MFN_400	1
305 
306 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
307 #define DP_MFD_216	(4 - 1)
308 #define DP_MFN_216	3
309 
310 #define CHIP_REV_1_0            0x10
311 #define CHIP_REV_1_1            0x11
312 #define CHIP_REV_2_0            0x20
313 #define CHIP_REV_2_5		0x25
314 #define CHIP_REV_3_0            0x30
315 
316 #define BOARD_REV_1_0           0x0
317 #define BOARD_REV_2_0           0x1
318 
319 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
320 
321 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
322 #include <asm/types.h>
323 
324 #define __REG(x)	(*((volatile u32 *)(x)))
325 #define __REG16(x)	(*((volatile u16 *)(x)))
326 #define __REG8(x)	(*((volatile u8 *)(x)))
327 
328 struct clkctl {
329 	u32	ccr;
330 	u32	ccdr;
331 	u32	csr;
332 	u32	ccsr;
333 	u32	cacrr;
334 	u32	cbcdr;
335 	u32	cbcmr;
336 	u32	cscmr1;
337 	u32	cscmr2;
338 	u32	cscdr1;
339 	u32	cs1cdr;
340 	u32	cs2cdr;
341 	u32	cdcdr;
342 	u32	chsccdr;
343 	u32	cscdr2;
344 	u32	cscdr3;
345 	u32	cscdr4;
346 	u32	cwdr;
347 	u32	cdhipr;
348 	u32	cdcr;
349 	u32	ctor;
350 	u32	clpcr;
351 	u32	cisr;
352 	u32	cimr;
353 	u32	ccosr;
354 	u32	cgpr;
355 	u32	ccgr0;
356 	u32	ccgr1;
357 	u32	ccgr2;
358 	u32	ccgr3;
359 	u32	ccgr4;
360 	u32	ccgr5;
361 	u32	ccgr6;
362 #if defined(CONFIG_MX53)
363 	u32	ccgr7;
364 #endif
365 	u32	cmeor;
366 };
367 
368 /* DPLL registers */
369 struct dpll {
370 	u32	dp_ctl;
371 	u32	dp_config;
372 	u32	dp_op;
373 	u32	dp_mfd;
374 	u32	dp_mfn;
375 	u32	dp_mfn_minus;
376 	u32	dp_mfn_plus;
377 	u32	dp_hfs_op;
378 	u32	dp_hfs_mfd;
379 	u32	dp_hfs_mfn;
380 	u32	dp_mfn_togc;
381 	u32	dp_destat;
382 };
383 /* WEIM registers */
384 struct weim {
385 	u32	cs0gcr1;
386 	u32	cs0gcr2;
387 	u32	cs0rcr1;
388 	u32	cs0rcr2;
389 	u32	cs0wcr1;
390 	u32	cs0wcr2;
391 	u32	cs1gcr1;
392 	u32	cs1gcr2;
393 	u32	cs1rcr1;
394 	u32	cs1rcr2;
395 	u32	cs1wcr1;
396 	u32	cs1wcr2;
397 	u32	cs2gcr1;
398 	u32	cs2gcr2;
399 	u32	cs2rcr1;
400 	u32	cs2rcr2;
401 	u32	cs2wcr1;
402 	u32	cs2wcr2;
403 	u32	cs3gcr1;
404 	u32	cs3gcr2;
405 	u32	cs3rcr1;
406 	u32	cs3rcr2;
407 	u32	cs3wcr1;
408 	u32	cs3wcr2;
409 	u32	cs4gcr1;
410 	u32	cs4gcr2;
411 	u32	cs4rcr1;
412 	u32	cs4rcr2;
413 	u32	cs4wcr1;
414 	u32	cs4wcr2;
415 	u32	cs5gcr1;
416 	u32	cs5gcr2;
417 	u32	cs5rcr1;
418 	u32	cs5rcr2;
419 	u32	cs5wcr1;
420 	u32	cs5wcr2;
421 	u32	wcr;
422 	u32	wiar;
423 	u32	ear;
424 };
425 
426 #if defined(CONFIG_MX51)
427 struct iomuxc {
428 	u32	gpr0;
429 	u32	gpr1;
430 	u32	omux0;
431 	u32	omux1;
432 	u32	omux2;
433 	u32	omux3;
434 	u32	omux4;
435 };
436 #elif defined(CONFIG_MX53)
437 struct iomuxc {
438 	u32	gpr0;
439 	u32	gpr1;
440 	u32	gpr2;
441 	u32	omux0;
442 	u32	omux1;
443 	u32	omux2;
444 	u32	omux3;
445 	u32	omux4;
446 };
447 #endif
448 
449 /* System Reset Controller (SRC) */
450 struct src {
451 	u32	scr;
452 	u32	sbmr;
453 	u32	srsr;
454 	u32	reserved1[2];
455 	u32	sisr;
456 	u32	simr;
457 };
458 
459 /* CSPI registers */
460 struct cspi_regs {
461 	u32 rxdata;
462 	u32 txdata;
463 	u32 ctrl;
464 	u32 cfg;
465 	u32 intr;
466 	u32 dma;
467 	u32 stat;
468 	u32 period;
469 };
470 
471 struct iim_regs {
472 	u32	stat;
473 	u32	statm;
474 	u32     err;
475 	u32	emask;
476 	u32	fctl;
477 	u32	ua;
478 	u32	la;
479 	u32	sdat;
480 	u32	prev;
481 	u32	srev;
482 	u32	preg_p;
483 	u32	scs0;
484 	u32	scs1;
485 	u32	scs2;
486 	u32	scs3;
487 	u32	res0[0x1f1];
488 	struct fuse_bank {
489 		u32	fuse_regs[0x20];
490 		u32	fuse_rsvd[0xe0];
491 	} bank[4];
492 };
493 
494 struct fuse_bank0_regs {
495 	u32	fuse0_23[24];
496 	u32	gp[8];
497 };
498 
499 struct fuse_bank1_regs {
500 	u32	fuse0_8[9];
501 	u32	mac_addr[6];
502 	u32	fuse15_31[0x11];
503 };
504 
505 #endif /* __ASSEMBLER__*/
506 
507 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
508