1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ 24 #define __ASM_ARCH_MX5_IMX_REGS_H__ 25 26 #if defined(CONFIG_MX51) 27 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 28 #define IPU_SOC_BASE_ADDR 0x40000000 29 #define IPU_SOC_OFFSET 0x1E000000 30 #define SPBA0_BASE_ADDR 0x70000000 31 #define AIPS1_BASE_ADDR 0x73F00000 32 #define AIPS2_BASE_ADDR 0x83F00000 33 #define CSD0_BASE_ADDR 0x90000000 34 #define CSD1_BASE_ADDR 0xA0000000 35 #define NFC_BASE_ADDR_AXI 0xCFFF0000 36 #define CS1_BASE_ADDR 0xB8000000 37 #elif defined(CONFIG_MX53) 38 #define IPU_SOC_BASE_ADDR 0x18000000 39 #define IPU_SOC_OFFSET 0x06000000 40 #define SPBA0_BASE_ADDR 0x50000000 41 #define AIPS1_BASE_ADDR 0x53F00000 42 #define AIPS2_BASE_ADDR 0x63F00000 43 #define CSD0_BASE_ADDR 0x70000000 44 #define CSD1_BASE_ADDR 0xB0000000 45 #define NFC_BASE_ADDR_AXI 0xF7FF0000 46 #define IRAM_BASE_ADDR 0xF8000000 47 #define CS1_BASE_ADDR 0xF4000000 48 #define SATA_BASE_ADDR 0x10000000 49 #else 50 #error "CPU_TYPE not defined" 51 #endif 52 53 #define IRAM_SIZE 0x00020000 /* 128 KB */ 54 55 /* 56 * SPBA global module enabled #0 57 */ 58 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 59 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 60 #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) 61 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 62 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 63 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 64 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 65 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 66 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 67 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 68 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 69 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 70 71 /* 72 * AIPS 1 73 */ 74 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 75 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 76 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 77 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 78 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 79 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 80 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 81 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 82 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 83 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 84 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 85 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 86 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 87 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 88 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 89 #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) 90 #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) 91 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 92 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 93 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 94 95 #if defined(CONFIG_MX53) 96 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) 97 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) 98 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) 99 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) 100 #endif 101 /* 102 * AIPS 2 103 */ 104 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 105 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 106 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 107 #ifdef CONFIG_MX53 108 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) 109 #endif 110 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 111 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 112 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 113 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 114 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 115 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 116 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 117 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 118 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 119 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 120 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 121 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 122 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 123 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 124 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 125 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 126 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 127 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 128 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 129 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 130 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 131 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 132 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 133 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 134 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 135 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 136 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 137 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 138 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 139 140 #if defined(CONFIG_MX53) 141 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) 142 #endif 143 144 /* 145 * WEIM CSnGCR1 146 */ 147 #define CSEN 1 148 #define SWR (1 << 1) 149 #define SRD (1 << 2) 150 #define MUM (1 << 3) 151 #define WFL (1 << 4) 152 #define RFL (1 << 5) 153 #define CRE (1 << 6) 154 #define CREP (1 << 7) 155 #define BL(x) (((x) & 0x7) << 8) 156 #define WC (1 << 11) 157 #define BCD(x) (((x) & 0x3) << 12) 158 #define BCS(x) (((x) & 0x3) << 14) 159 #define DSZ(x) (((x) & 0x7) << 16) 160 #define SP (1 << 19) 161 #define CSREC(x) (((x) & 0x7) << 20) 162 #define AUS (1 << 23) 163 #define GBC(x) (((x) & 0x7) << 24) 164 #define WP (1 << 27) 165 #define PSZ(x) (((x) & 0x0f << 28) 166 167 /* 168 * WEIM CSnGCR2 169 */ 170 #define ADH(x) (((x) & 0x3)) 171 #define DAPS(x) (((x) & 0x0f << 4) 172 #define DAE (1 << 8) 173 #define DAP (1 << 9) 174 #define MUX16_BYP (1 << 12) 175 176 /* 177 * WEIM CSnRCR1 178 */ 179 #define RCSN(x) (((x) & 0x7)) 180 #define RCSA(x) (((x) & 0x7) << 4) 181 #define OEN(x) (((x) & 0x7) << 8) 182 #define OEA(x) (((x) & 0x7) << 12) 183 #define RADVN(x) (((x) & 0x7) << 16) 184 #define RAL (1 << 19) 185 #define RADVA(x) (((x) & 0x7) << 20) 186 #define RWSC(x) (((x) & 0x3f) << 24) 187 188 /* 189 * WEIM CSnRCR2 190 */ 191 #define RBEN(x) (((x) & 0x7)) 192 #define RBE (1 << 3) 193 #define RBEA(x) (((x) & 0x7) << 4) 194 #define RL(x) (((x) & 0x3) << 8) 195 #define PAT(x) (((x) & 0x7) << 12) 196 #define APR (1 << 15) 197 198 /* 199 * WEIM CSnWCR1 200 */ 201 #define WCSN(x) (((x) & 0x7)) 202 #define WCSA(x) (((x) & 0x7) << 3) 203 #define WEN(x) (((x) & 0x7) << 6) 204 #define WEA(x) (((x) & 0x7) << 9) 205 #define WBEN(x) (((x) & 0x7) << 12) 206 #define WBEA(x) (((x) & 0x7) << 15) 207 #define WADVN(x) (((x) & 0x7) << 18) 208 #define WADVA(x) (((x) & 0x7) << 21) 209 #define WWSC(x) (((x) & 0x3f) << 24) 210 #define WBED1 (1 << 30) 211 #define WAL (1 << 31) 212 213 /* 214 * WEIM CSnWCR2 215 */ 216 #define WBED 1 217 218 /* 219 * WEIM WCR 220 */ 221 #define BCM 1 222 #define GBCD(x) (((x) & 0x3) << 1) 223 #define INTEN (1 << 4) 224 #define INTPOL (1 << 5) 225 #define WDOG_EN (1 << 8) 226 #define WDOG_LIMIT(x) (((x) & 0x3) << 9) 227 228 #define CS0_128 0 229 #define CS0_64M_CS1_64M 1 230 #define CS0_64M_CS1_32M_CS2_32M 2 231 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 232 233 /* 234 * CSPI register definitions 235 */ 236 #define MXC_ECSPI 237 #define MXC_CSPICTRL_EN (1 << 0) 238 #define MXC_CSPICTRL_MODE (1 << 1) 239 #define MXC_CSPICTRL_XCH (1 << 2) 240 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 241 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 242 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 243 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 244 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 245 #define MXC_CSPICTRL_MAXBITS 0xfff 246 #define MXC_CSPICTRL_TC (1 << 7) 247 #define MXC_CSPICTRL_RXOVF (1 << 6) 248 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 249 #define MAX_SPI_BYTES 32 250 251 /* Bit position inside CTRL register to be associated with SS */ 252 #define MXC_CSPICTRL_CHAN 18 253 254 /* Bit position inside CON register to be associated with SS */ 255 #define MXC_CSPICON_POL 4 256 #define MXC_CSPICON_PHA 0 257 #define MXC_CSPICON_SSPOL 12 258 #define MXC_SPI_BASE_ADDRESSES \ 259 CSPI1_BASE_ADDR, \ 260 CSPI2_BASE_ADDR, \ 261 CSPI3_BASE_ADDR, 262 263 /* 264 * Number of GPIO pins per port 265 */ 266 #define GPIO_NUM_PIN 32 267 268 #define IIM_SREV 0x24 269 #define ROM_SI_REV 0x48 270 271 #define NFC_BUF_SIZE 0x1000 272 273 /* M4IF */ 274 #define M4IF_FBPM0 0x40 275 #define M4IF_FIDBP 0x48 276 277 /* Assuming 24MHz input clock with doubler ON */ 278 /* MFI PDF */ 279 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) 280 #define DP_MFD_864 (180 - 1) /* PL Dither mode */ 281 #define DP_MFN_864 180 282 #define DP_MFN_800_DIT 60 /* PL Dither mode */ 283 284 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 285 #define DP_MFD_850 (48 - 1) 286 #define DP_MFN_850 41 287 288 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 289 #define DP_MFD_800 (3 - 1) 290 #define DP_MFN_800 1 291 292 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 293 #define DP_MFD_700 (24 - 1) 294 #define DP_MFN_700 7 295 296 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 297 #define DP_MFD_665 (96 - 1) 298 #define DP_MFN_665 89 299 300 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 301 #define DP_MFD_532 (24 - 1) 302 #define DP_MFN_532 13 303 304 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 305 #define DP_MFD_400 (3 - 1) 306 #define DP_MFN_400 1 307 308 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 309 #define DP_MFD_216 (4 - 1) 310 #define DP_MFN_216 3 311 312 #define CHIP_REV_1_0 0x10 313 #define CHIP_REV_1_1 0x11 314 #define CHIP_REV_2_0 0x20 315 #define CHIP_REV_2_5 0x25 316 #define CHIP_REV_3_0 0x30 317 318 #define BOARD_REV_1_0 0x0 319 #define BOARD_REV_2_0 0x1 320 321 #define IMX_IIM_BASE (IIM_BASE_ADDR) 322 323 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 324 #include <asm/types.h> 325 326 #define __REG(x) (*((volatile u32 *)(x))) 327 #define __REG16(x) (*((volatile u16 *)(x))) 328 #define __REG8(x) (*((volatile u8 *)(x))) 329 330 struct clkctl { 331 u32 ccr; 332 u32 ccdr; 333 u32 csr; 334 u32 ccsr; 335 u32 cacrr; 336 u32 cbcdr; 337 u32 cbcmr; 338 u32 cscmr1; 339 u32 cscmr2; 340 u32 cscdr1; 341 u32 cs1cdr; 342 u32 cs2cdr; 343 u32 cdcdr; 344 u32 chsccdr; 345 u32 cscdr2; 346 u32 cscdr3; 347 u32 cscdr4; 348 u32 cwdr; 349 u32 cdhipr; 350 u32 cdcr; 351 u32 ctor; 352 u32 clpcr; 353 u32 cisr; 354 u32 cimr; 355 u32 ccosr; 356 u32 cgpr; 357 u32 ccgr0; 358 u32 ccgr1; 359 u32 ccgr2; 360 u32 ccgr3; 361 u32 ccgr4; 362 u32 ccgr5; 363 u32 ccgr6; 364 #if defined(CONFIG_MX53) 365 u32 ccgr7; 366 #endif 367 u32 cmeor; 368 }; 369 370 /* DPLL registers */ 371 struct dpll { 372 u32 dp_ctl; 373 u32 dp_config; 374 u32 dp_op; 375 u32 dp_mfd; 376 u32 dp_mfn; 377 u32 dp_mfn_minus; 378 u32 dp_mfn_plus; 379 u32 dp_hfs_op; 380 u32 dp_hfs_mfd; 381 u32 dp_hfs_mfn; 382 u32 dp_mfn_togc; 383 u32 dp_destat; 384 }; 385 /* WEIM registers */ 386 struct weim { 387 u32 cs0gcr1; 388 u32 cs0gcr2; 389 u32 cs0rcr1; 390 u32 cs0rcr2; 391 u32 cs0wcr1; 392 u32 cs0wcr2; 393 u32 cs1gcr1; 394 u32 cs1gcr2; 395 u32 cs1rcr1; 396 u32 cs1rcr2; 397 u32 cs1wcr1; 398 u32 cs1wcr2; 399 u32 cs2gcr1; 400 u32 cs2gcr2; 401 u32 cs2rcr1; 402 u32 cs2rcr2; 403 u32 cs2wcr1; 404 u32 cs2wcr2; 405 u32 cs3gcr1; 406 u32 cs3gcr2; 407 u32 cs3rcr1; 408 u32 cs3rcr2; 409 u32 cs3wcr1; 410 u32 cs3wcr2; 411 u32 cs4gcr1; 412 u32 cs4gcr2; 413 u32 cs4rcr1; 414 u32 cs4rcr2; 415 u32 cs4wcr1; 416 u32 cs4wcr2; 417 u32 cs5gcr1; 418 u32 cs5gcr2; 419 u32 cs5rcr1; 420 u32 cs5rcr2; 421 u32 cs5wcr1; 422 u32 cs5wcr2; 423 u32 wcr; 424 u32 wiar; 425 u32 ear; 426 }; 427 428 #if defined(CONFIG_MX51) 429 struct iomuxc { 430 u32 gpr0; 431 u32 gpr1; 432 u32 omux0; 433 u32 omux1; 434 u32 omux2; 435 u32 omux3; 436 u32 omux4; 437 }; 438 #elif defined(CONFIG_MX53) 439 struct iomuxc { 440 u32 gpr0; 441 u32 gpr1; 442 u32 gpr2; 443 u32 omux0; 444 u32 omux1; 445 u32 omux2; 446 u32 omux3; 447 u32 omux4; 448 }; 449 #endif 450 451 /* System Reset Controller (SRC) */ 452 struct src { 453 u32 scr; 454 u32 sbmr; 455 u32 srsr; 456 u32 reserved1[2]; 457 u32 sisr; 458 u32 simr; 459 }; 460 461 /* CSPI registers */ 462 struct cspi_regs { 463 u32 rxdata; 464 u32 txdata; 465 u32 ctrl; 466 u32 cfg; 467 u32 intr; 468 u32 dma; 469 u32 stat; 470 u32 period; 471 }; 472 473 struct iim_regs { 474 u32 stat; 475 u32 statm; 476 u32 err; 477 u32 emask; 478 u32 fctl; 479 u32 ua; 480 u32 la; 481 u32 sdat; 482 u32 prev; 483 u32 srev; 484 u32 preg_p; 485 u32 scs0; 486 u32 scs1; 487 u32 scs2; 488 u32 scs3; 489 u32 res0[0x1f1]; 490 struct fuse_bank { 491 u32 fuse_regs[0x20]; 492 u32 fuse_rsvd[0xe0]; 493 } bank[4]; 494 }; 495 496 struct fuse_bank0_regs { 497 u32 fuse0_23[24]; 498 u32 gp[8]; 499 }; 500 501 struct fuse_bank1_regs { 502 u32 fuse0_8[9]; 503 u32 mac_addr[6]; 504 u32 fuse15_31[0x11]; 505 }; 506 507 #endif /* __ASSEMBLER__*/ 508 509 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ 510