1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
25 
26 #define ARCH_MXC
27 
28 #if defined(CONFIG_MX51)
29 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
30 #define IPU_SOC_BASE_ADDR	0x40000000
31 #define IPU_SOC_OFFSET		0x1E000000
32 #define SPBA0_BASE_ADDR         0x70000000
33 #define AIPS1_BASE_ADDR         0x73F00000
34 #define AIPS2_BASE_ADDR         0x83F00000
35 #define CSD0_BASE_ADDR          0x90000000
36 #define CSD1_BASE_ADDR          0xA0000000
37 #define NFC_BASE_ADDR_AXI       0xCFFF0000
38 #define CS1_BASE_ADDR           0xB8000000
39 #elif defined(CONFIG_MX53)
40 #define IPU_SOC_BASE_ADDR	0x18000000
41 #define IPU_SOC_OFFSET		0x06000000
42 #define SPBA0_BASE_ADDR         0x50000000
43 #define AIPS1_BASE_ADDR         0x53F00000
44 #define AIPS2_BASE_ADDR         0x63F00000
45 #define CSD0_BASE_ADDR          0x70000000
46 #define CSD1_BASE_ADDR          0xB0000000
47 #define NFC_BASE_ADDR_AXI       0xF7FF0000
48 #define IRAM_BASE_ADDR          0xF8000000
49 #define CS1_BASE_ADDR           0xF4000000
50 #define SATA_BASE_ADDR		0x10000000
51 #else
52 #error "CPU_TYPE not defined"
53 #endif
54 
55 #define IRAM_SIZE		0x00020000	/* 128 KB */
56 
57 /*
58  * SPBA global module enabled #0
59  */
60 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
61 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
62 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
63 #define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
64 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
65 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
66 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
67 #define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
68 #define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
69 #define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
70 #define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
71 #define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
72 
73 /*
74  * AIPS 1
75  */
76 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
77 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
78 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
79 #define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
80 #define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
81 #define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
82 #define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
83 #define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
84 #define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
85 #define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
86 #define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
87 #define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
88 #define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
89 #define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
90 #define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
91 #define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
92 #define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
93 #define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
94 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
95 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
96 
97 #if defined(CONFIG_MX53)
98 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
99 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
100 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
101 #define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
102 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
103 #endif
104 /*
105  * AIPS 2
106  */
107 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
108 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
109 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
110 #ifdef	CONFIG_MX53
111 #define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
112 #endif
113 #define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
114 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
115 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
116 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
117 #define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
118 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
119 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
120 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
121 #define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
122 #define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
123 #define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
124 #define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
125 #define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
126 #define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
127 #define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
128 #define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
129 #define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
130 #define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
131 #define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
132 #define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
133 #define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
134 #define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
135 #define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
136 #define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
137 #define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
138 #define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
139 #define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
140 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
141 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
142 
143 #if defined(CONFIG_MX53)
144 #define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
145 #endif
146 
147 /*
148  * WEIM CSnGCR1
149  */
150 #define CSEN		1
151 #define SWR		(1 << 1)
152 #define SRD		(1 << 2)
153 #define MUM		(1 << 3)
154 #define WFL		(1 << 4)
155 #define RFL		(1 << 5)
156 #define CRE		(1 << 6)
157 #define CREP		(1 << 7)
158 #define BL(x)		(((x) & 0x7) << 8)
159 #define WC		(1 << 11)
160 #define BCD(x)		(((x) & 0x3) << 12)
161 #define BCS(x)		(((x) & 0x3) << 14)
162 #define DSZ(x)		(((x) & 0x7) << 16)
163 #define SP		(1 << 19)
164 #define CSREC(x)	(((x) & 0x7) << 20)
165 #define AUS		(1 << 23)
166 #define GBC(x)		(((x) & 0x7) << 24)
167 #define WP		(1 << 27)
168 #define PSZ(x)		(((x) & 0x0f << 28)
169 
170 /*
171  * WEIM CSnGCR2
172  */
173 #define ADH(x)		(((x) & 0x3))
174 #define DAPS(x)		(((x) & 0x0f << 4)
175 #define DAE		(1 << 8)
176 #define DAP		(1 << 9)
177 #define MUX16_BYP	(1 << 12)
178 
179 /*
180  * WEIM CSnRCR1
181  */
182 #define RCSN(x)		(((x) & 0x7))
183 #define RCSA(x)		(((x) & 0x7) << 4)
184 #define OEN(x)		(((x) & 0x7) << 8)
185 #define OEA(x)		(((x) & 0x7) << 12)
186 #define RADVN(x)	(((x) & 0x7) << 16)
187 #define RAL		(1 << 19)
188 #define RADVA(x)	(((x) & 0x7) << 20)
189 #define RWSC(x)		(((x) & 0x3f) << 24)
190 
191 /*
192  * WEIM CSnRCR2
193  */
194 #define RBEN(x)		(((x) & 0x7))
195 #define RBE		(1 << 3)
196 #define RBEA(x)		(((x) & 0x7) << 4)
197 #define RL(x)		(((x) & 0x3) << 8)
198 #define PAT(x)		(((x) & 0x7) << 12)
199 #define APR		(1 << 15)
200 
201 /*
202  * WEIM CSnWCR1
203  */
204 #define WCSN(x)		(((x) & 0x7))
205 #define WCSA(x)		(((x) & 0x7) << 3)
206 #define WEN(x)		(((x) & 0x7) << 6)
207 #define WEA(x)		(((x) & 0x7) << 9)
208 #define WBEN(x)		(((x) & 0x7) << 12)
209 #define WBEA(x)		(((x) & 0x7) << 15)
210 #define WADVN(x)	(((x) & 0x7) << 18)
211 #define WADVA(x)	(((x) & 0x7) << 21)
212 #define WWSC(x)		(((x) & 0x3f) << 24)
213 #define WBED1		(1 << 30)
214 #define WAL		(1 << 31)
215 
216 /*
217  * WEIM CSnWCR2
218  */
219 #define WBED		1
220 
221 /*
222  * WEIM WCR
223  */
224 #define BCM		1
225 #define GBCD(x)		(((x) & 0x3) << 1)
226 #define INTEN		(1 << 4)
227 #define INTPOL		(1 << 5)
228 #define WDOG_EN		(1 << 8)
229 #define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
230 
231 #define CS0_128					0
232 #define CS0_64M_CS1_64M				1
233 #define CS0_64M_CS1_32M_CS2_32M			2
234 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
235 
236 /*
237  * CSPI register definitions
238  */
239 #define MXC_ECSPI
240 #define MXC_CSPICTRL_EN		(1 << 0)
241 #define MXC_CSPICTRL_MODE	(1 << 1)
242 #define MXC_CSPICTRL_XCH	(1 << 2)
243 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
244 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
245 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
246 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
247 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
248 #define MXC_CSPICTRL_MAXBITS	0xfff
249 #define MXC_CSPICTRL_TC		(1 << 7)
250 #define MXC_CSPICTRL_RXOVF	(1 << 6)
251 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
252 #define MAX_SPI_BYTES	32
253 
254 /* Bit position inside CTRL register to be associated with SS */
255 #define MXC_CSPICTRL_CHAN	18
256 
257 /* Bit position inside CON register to be associated with SS */
258 #define MXC_CSPICON_POL		4
259 #define MXC_CSPICON_PHA		0
260 #define MXC_CSPICON_SSPOL	12
261 #define MXC_SPI_BASE_ADDRESSES \
262 	CSPI1_BASE_ADDR, \
263 	CSPI2_BASE_ADDR, \
264 	CSPI3_BASE_ADDR,
265 
266 /*
267  * Number of GPIO pins per port
268  */
269 #define GPIO_NUM_PIN            32
270 
271 #define IIM_SREV	0x24
272 #define ROM_SI_REV	0x48
273 
274 #define NFC_BUF_SIZE	0x1000
275 
276 /* M4IF */
277 #define M4IF_FBPM0	0x40
278 #define M4IF_FIDBP	0x48
279 
280 /* Assuming 24MHz input clock with doubler ON */
281 /*                            MFI         PDF */
282 #define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
283 #define DP_MFD_864	(180 - 1) /* PL Dither mode */
284 #define DP_MFN_864	180
285 #define DP_MFN_800_DIT	60 /* PL Dither mode */
286 
287 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
288 #define DP_MFD_850	(48 - 1)
289 #define DP_MFN_850	41
290 
291 #define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
292 #define DP_MFD_800	(3 - 1)
293 #define DP_MFN_800	1
294 
295 #define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
296 #define DP_MFD_700	(24 - 1)
297 #define DP_MFN_700	7
298 
299 #define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
300 #define DP_MFD_665	(96 - 1)
301 #define DP_MFN_665	89
302 
303 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
304 #define DP_MFD_532	(24 - 1)
305 #define DP_MFN_532	13
306 
307 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
308 #define DP_MFD_400	(3 - 1)
309 #define DP_MFN_400	1
310 
311 #define DP_OP_455	((9 << 4) + ((2 - 1)  << 0))
312 #define DP_MFD_455	(48 - 1)
313 #define DP_MFN_455	23
314 
315 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
316 #define DP_MFD_216	(4 - 1)
317 #define DP_MFN_216	3
318 
319 #define CHIP_REV_1_0            0x10
320 #define CHIP_REV_1_1            0x11
321 #define CHIP_REV_2_0            0x20
322 #define CHIP_REV_2_5		0x25
323 #define CHIP_REV_3_0            0x30
324 
325 #define BOARD_REV_1_0           0x0
326 #define BOARD_REV_2_0           0x1
327 
328 #define BOARD_VER_OFFSET	0x8
329 
330 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
331 
332 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
333 #include <asm/types.h>
334 
335 #define __REG(x)	(*((volatile u32 *)(x)))
336 #define __REG16(x)	(*((volatile u16 *)(x)))
337 #define __REG8(x)	(*((volatile u8 *)(x)))
338 
339 struct clkctl {
340 	u32	ccr;
341 	u32	ccdr;
342 	u32	csr;
343 	u32	ccsr;
344 	u32	cacrr;
345 	u32	cbcdr;
346 	u32	cbcmr;
347 	u32	cscmr1;
348 	u32	cscmr2;
349 	u32	cscdr1;
350 	u32	cs1cdr;
351 	u32	cs2cdr;
352 	u32	cdcdr;
353 	u32	chsccdr;
354 	u32	cscdr2;
355 	u32	cscdr3;
356 	u32	cscdr4;
357 	u32	cwdr;
358 	u32	cdhipr;
359 	u32	cdcr;
360 	u32	ctor;
361 	u32	clpcr;
362 	u32	cisr;
363 	u32	cimr;
364 	u32	ccosr;
365 	u32	cgpr;
366 	u32	ccgr0;
367 	u32	ccgr1;
368 	u32	ccgr2;
369 	u32	ccgr3;
370 	u32	ccgr4;
371 	u32	ccgr5;
372 	u32	ccgr6;
373 #if defined(CONFIG_MX53)
374 	u32	ccgr7;
375 #endif
376 	u32	cmeor;
377 };
378 
379 /* DPLL registers */
380 struct dpll {
381 	u32	dp_ctl;
382 	u32	dp_config;
383 	u32	dp_op;
384 	u32	dp_mfd;
385 	u32	dp_mfn;
386 	u32	dp_mfn_minus;
387 	u32	dp_mfn_plus;
388 	u32	dp_hfs_op;
389 	u32	dp_hfs_mfd;
390 	u32	dp_hfs_mfn;
391 	u32	dp_mfn_togc;
392 	u32	dp_destat;
393 };
394 /* WEIM registers */
395 struct weim {
396 	u32	cs0gcr1;
397 	u32	cs0gcr2;
398 	u32	cs0rcr1;
399 	u32	cs0rcr2;
400 	u32	cs0wcr1;
401 	u32	cs0wcr2;
402 	u32	cs1gcr1;
403 	u32	cs1gcr2;
404 	u32	cs1rcr1;
405 	u32	cs1rcr2;
406 	u32	cs1wcr1;
407 	u32	cs1wcr2;
408 	u32	cs2gcr1;
409 	u32	cs2gcr2;
410 	u32	cs2rcr1;
411 	u32	cs2rcr2;
412 	u32	cs2wcr1;
413 	u32	cs2wcr2;
414 	u32	cs3gcr1;
415 	u32	cs3gcr2;
416 	u32	cs3rcr1;
417 	u32	cs3rcr2;
418 	u32	cs3wcr1;
419 	u32	cs3wcr2;
420 	u32	cs4gcr1;
421 	u32	cs4gcr2;
422 	u32	cs4rcr1;
423 	u32	cs4rcr2;
424 	u32	cs4wcr1;
425 	u32	cs4wcr2;
426 	u32	cs5gcr1;
427 	u32	cs5gcr2;
428 	u32	cs5rcr1;
429 	u32	cs5rcr2;
430 	u32	cs5wcr1;
431 	u32	cs5wcr2;
432 	u32	wcr;
433 	u32	wiar;
434 	u32	ear;
435 };
436 
437 #if defined(CONFIG_MX51)
438 struct iomuxc {
439 	u32	gpr0;
440 	u32	gpr1;
441 	u32	omux0;
442 	u32	omux1;
443 	u32	omux2;
444 	u32	omux3;
445 	u32	omux4;
446 };
447 #elif defined(CONFIG_MX53)
448 struct iomuxc {
449 	u32	gpr0;
450 	u32	gpr1;
451 	u32	gpr2;
452 	u32	omux0;
453 	u32	omux1;
454 	u32	omux2;
455 	u32	omux3;
456 	u32	omux4;
457 };
458 #endif
459 
460 /* System Reset Controller (SRC) */
461 struct src {
462 	u32	scr;
463 	u32	sbmr;
464 	u32	srsr;
465 	u32	reserved1[2];
466 	u32	sisr;
467 	u32	simr;
468 };
469 
470 struct srtc_regs {
471 	u32	lpscmr;		/* 0x00 */
472 	u32	lpsclr;		/* 0x04 */
473 	u32	lpsar;		/* 0x08 */
474 	u32	lpsmcr;		/* 0x0c */
475 	u32	lpcr;		/* 0x10 */
476 	u32	lpsr;		/* 0x14 */
477 	u32	lppdr;		/* 0x18 */
478 	u32	lpgr;		/* 0x1c */
479 	u32	hpcmr;		/* 0x20 */
480 	u32	hpclr;		/* 0x24 */
481 	u32	hpamr;		/* 0x28 */
482 	u32	hpalr;		/* 0x2c */
483 	u32	hpcr;		/* 0x30 */
484 	u32	hpisr;		/* 0x34 */
485 	u32	hpienr;		/* 0x38 */
486 };
487 
488 /* CSPI registers */
489 struct cspi_regs {
490 	u32 rxdata;
491 	u32 txdata;
492 	u32 ctrl;
493 	u32 cfg;
494 	u32 intr;
495 	u32 dma;
496 	u32 stat;
497 	u32 period;
498 };
499 
500 struct iim_regs {
501 	u32	stat;
502 	u32	statm;
503 	u32     err;
504 	u32	emask;
505 	u32	fctl;
506 	u32	ua;
507 	u32	la;
508 	u32	sdat;
509 	u32	prev;
510 	u32	srev;
511 	u32	preg_p;
512 	u32	scs0;
513 	u32	scs1;
514 	u32	scs2;
515 	u32	scs3;
516 	u32	res0[0x1f1];
517 	struct fuse_bank {
518 		u32	fuse_regs[0x20];
519 		u32	fuse_rsvd[0xe0];
520 	} bank[4];
521 };
522 
523 struct fuse_bank0_regs {
524 	u32	fuse0_23[24];
525 	u32	gp[8];
526 };
527 
528 struct fuse_bank1_regs {
529 	u32	fuse0_8[9];
530 	u32	mac_addr[6];
531 	u32	fuse15_31[0x11];
532 };
533 
534 #endif /* __ASSEMBLER__*/
535 
536 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
537