1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
25 
26 #if defined(CONFIG_MX51)
27 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
28 #define IPU_CTRL_BASE_ADDR	0x40000000
29 #define SPBA0_BASE_ADDR         0x70000000
30 #define AIPS1_BASE_ADDR         0x73F00000
31 #define AIPS2_BASE_ADDR         0x83F00000
32 #define CSD0_BASE_ADDR          0x90000000
33 #define CSD1_BASE_ADDR          0xA0000000
34 #define NFC_BASE_ADDR_AXI       0xCFFF0000
35 #elif defined(CONFIG_MX53)
36 #define IPU_CTRL_BASE_ADDR      0x18000000
37 #define SPBA0_BASE_ADDR         0x50000000
38 #define AIPS1_BASE_ADDR         0x53F00000
39 #define AIPS2_BASE_ADDR         0x63F00000
40 #define CSD0_BASE_ADDR          0x70000000
41 #define CSD1_BASE_ADDR          0xB0000000
42 #define NFC_BASE_ADDR_AXI       0xF7FF0000
43 #define IRAM_BASE_ADDR          0xF8000000
44 #else
45 #error "CPU_TYPE not defined"
46 #endif
47 
48 #define IRAM_SIZE		0x00020000	/* 128 KB */
49 
50 /*
51  * SPBA global module enabled #0
52  */
53 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
54 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
55 #define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
56 #define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
57 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
58 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
59 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
60 #define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
61 #define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
62 #define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
63 #define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
64 #define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
65 
66 /*
67  * AIPS 1
68  */
69 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
70 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
71 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
72 #define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
73 #define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
74 #define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
75 #define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
76 #define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
77 #define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
78 #define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
79 #define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
80 #define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
81 #define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
82 #define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
83 #define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
84 #define UART1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000BC000)
85 #define UART2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000C0000)
86 #define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
87 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
88 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
89 
90 #if defined(CONFIG_MX53)
91 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
92 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
93 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
94 #endif
95 /*
96  * AIPS 2
97  */
98 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
99 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
100 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
101 #define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
102 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
103 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
104 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
105 #define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
106 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
107 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
108 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
109 #define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
110 #define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
111 #define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
112 #define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
113 #define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
114 #define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
115 #define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
116 #define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
117 #define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
118 #define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
119 #define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
120 #define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
121 #define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
122 #define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
123 #define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
124 #define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
125 #define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
126 #define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
127 #define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
128 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
129 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
130 
131 /*
132  * Number of GPIO pins per port
133  */
134 #define GPIO_NUM_PIN            32
135 
136 #define IIM_SREV	0x24
137 #define ROM_SI_REV	0x48
138 
139 #define NFC_BUF_SIZE	0x1000
140 
141 /* M4IF */
142 #define M4IF_FBPM0	0x40
143 #define M4IF_FIDBP	0x48
144 
145 /* Assuming 24MHz input clock with doubler ON */
146 /*                            MFI         PDF */
147 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
148 #define DP_MFD_850	(48 - 1)
149 #define DP_MFN_850	41
150 
151 #define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
152 #define DP_MFD_800	(3 - 1)
153 #define DP_MFN_800	1
154 
155 #define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
156 #define DP_MFD_700	(24 - 1)
157 #define DP_MFN_700	7
158 
159 #define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
160 #define DP_MFD_665	(96 - 1)
161 #define DP_MFN_665	89
162 
163 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
164 #define DP_MFD_532	(24 - 1)
165 #define DP_MFN_532	13
166 
167 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
168 #define DP_MFD_400	(3 - 1)
169 #define DP_MFN_400	1
170 
171 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
172 #define DP_MFD_216	(4 - 1)
173 #define DP_MFN_216	3
174 
175 #define CHIP_REV_1_0            0x10
176 #define CHIP_REV_1_1            0x11
177 #define CHIP_REV_2_0            0x20
178 #define CHIP_REV_2_5		0x25
179 #define CHIP_REV_3_0            0x30
180 
181 #define BOARD_REV_1_0           0x0
182 #define BOARD_REV_2_0           0x1
183 
184 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
185 
186 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
187 #include <asm/types.h>
188 
189 extern void imx_get_mac_from_fuse(unsigned char *mac);
190 
191 #define __REG(x)	(*((volatile u32 *)(x)))
192 #define __REG16(x)	(*((volatile u16 *)(x)))
193 #define __REG8(x)	(*((volatile u8 *)(x)))
194 
195 struct clkctl {
196 	u32	ccr;
197 	u32	ccdr;
198 	u32	csr;
199 	u32	ccsr;
200 	u32	cacrr;
201 	u32	cbcdr;
202 	u32	cbcmr;
203 	u32	cscmr1;
204 	u32	cscmr2;
205 	u32	cscdr1;
206 	u32	cs1cdr;
207 	u32	cs2cdr;
208 	u32	cdcdr;
209 	u32	chsccdr;
210 	u32	cscdr2;
211 	u32	cscdr3;
212 	u32	cscdr4;
213 	u32	cwdr;
214 	u32	cdhipr;
215 	u32	cdcr;
216 	u32	ctor;
217 	u32	clpcr;
218 	u32	cisr;
219 	u32	cimr;
220 	u32	ccosr;
221 	u32	cgpr;
222 	u32	ccgr0;
223 	u32	ccgr1;
224 	u32	ccgr2;
225 	u32	ccgr3;
226 	u32	ccgr4;
227 	u32	ccgr5;
228 	u32	ccgr6;
229 	u32	cmeor;
230 };
231 
232 /* WEIM registers */
233 struct weim {
234 	u32	csgcr1;
235 	u32	csgcr2;
236 	u32	csrcr1;
237 	u32	csrcr2;
238 	u32	cswcr1;
239 	u32	cswcr2;
240 };
241 
242 /* GPIO Registers */
243 struct gpio_regs {
244 	u32	gpio_dr;
245 	u32	gpio_dir;
246 	u32	gpio_psr;
247 };
248 
249 /* System Reset Controller (SRC) */
250 struct src {
251 	u32	scr;
252 	u32	sbmr;
253 	u32	srsr;
254 	u32	reserved1[2];
255 	u32	sisr;
256 	u32	simr;
257 };
258 
259 /* CSPI registers */
260 struct cspi_regs {
261 	u32 rxdata;
262 	u32 txdata;
263 	u32 ctrl;
264 	u32 cfg;
265 	u32 intr;
266 	u32 dma;
267 	u32 stat;
268 	u32 period;
269 };
270 
271 struct iim_regs {
272 	u32	stat;
273 	u32	statm;
274 	u32     err;
275 	u32	emask;
276 	u32	fctl;
277 	u32	ua;
278 	u32	la;
279 	u32	sdat;
280 	u32	prev;
281 	u32	srev;
282 	u32	preg_p;
283 	u32	scs0;
284 	u32	scs1;
285 	u32	scs2;
286 	u32	scs3;
287 	u32	res0[0x1f1];
288 	struct fuse_bank {
289 		u32	fuse_regs[0x20];
290 		u32	fuse_rsvd[0xe0];
291 	} bank[4];
292 };
293 
294 struct fuse_bank1_regs {
295 	u32	fuse0_8[9];
296 	u32	mac_addr[6];
297 	u32	fuse15_31[0x11];
298 };
299 
300 #endif /* __ASSEMBLER__*/
301 
302 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
303