xref: /openbmc/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h (revision 834a45d7ee81ef185cc834b44b2dae7b637631e2)
1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __ASM_ARCH_MXC_MX51_H__
24 #define __ASM_ARCH_MXC_MX51_H__
25 
26 /*
27  * IRAM
28  */
29 #define IRAM_BASE_ADDR		0x1FFE8000	/* internal ram */
30 /*
31  * Graphics Memory of GPU
32  */
33 #define GPU_BASE_ADDR		0x20000000
34 #define GPU_CTRL_BASE_ADDR	0x30000000
35 #define IPU_CTRL_BASE_ADDR	0x40000000
36 /*
37  * Debug
38  */
39 #define DEBUG_BASE_ADDR		0x60000000
40 #define ETB_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00001000)
41 #define ETM_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00002000)
42 #define TPIU_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00003000)
43 #define CTI0_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00004000)
44 #define CTI1_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00005000)
45 #define CTI2_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00006000)
46 #define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
47 #define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
48 
49 /*
50  * SPBA global module enabled #0
51  */
52 #define SPBA0_BASE_ADDR 	0x70000000
53 
54 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
55 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
56 #define UART3_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x0000C000)
57 #define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
58 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
59 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
60 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
61 #define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
62 #define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
63 #define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
64 #define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
65 #define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
66 
67 /*
68  * AIPS 1
69  */
70 #define AIPS1_BASE_ADDR 	0x73F00000
71 
72 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
73 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
74 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
75 #define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
76 #define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
77 #define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
78 #define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
79 #define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
80 #define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
81 #define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
82 #define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
83 #define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
84 #define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
85 #define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
86 #define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
87 #define UART1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000BC000)
88 #define UART2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000C0000)
89 #define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
90 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
91 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
92 
93 /*
94  * AIPS 2
95  */
96 #define AIPS2_BASE_ADDR	0x83F00000
97 
98 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
99 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
100 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
101 #define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
102 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
103 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
104 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
105 #define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
106 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
107 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
108 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
109 #define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
110 #define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
111 #define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
112 #define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
113 #define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
114 #define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
115 #define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
116 #define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
117 #define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
118 #define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
119 #define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
120 #define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
121 #define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
122 #define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
123 #define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
124 #define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
125 #define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
126 #define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
127 #define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
128 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
129 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
130 
131 #define TZIC_BASE_ADDR		0x8FFFC000
132 
133 /*
134  * Memory regions and CS
135  */
136 #define CSD0_BASE_ADDR		0x90000000
137 #define CSD1_BASE_ADDR		0xA0000000
138 #define CS0_BASE_ADDR		0xB0000000
139 #define CS1_BASE_ADDR		0xB8000000
140 #define CS2_BASE_ADDR		0xC0000000
141 #define CS3_BASE_ADDR		0xC8000000
142 #define CS4_BASE_ADDR		0xCC000000
143 #define CS5_BASE_ADDR		0xCE000000
144 
145 /*
146  * NFC
147  */
148 #define NFC_BASE_ADDR_AXI	0xCFFF0000	/* NAND flash AXI */
149 
150 /*!
151  * Number of GPIO port as defined in the IC Spec
152  */
153 #define GPIO_PORT_NUM		4
154 /*!
155  * Number of GPIO pins per port
156  */
157 #define GPIO_NUM_PIN            32
158 
159 #define IIM_SREV	0x24
160 #define ROM_SI_REV	0x48
161 
162 #define NFC_BUF_SIZE	0x1000
163 
164 /* M4IF */
165 #define M4IF_FBPM0	0x40
166 #define M4IF_FIDBP	0x48
167 
168 /* Assuming 24MHz input clock with doubler ON */
169 /*                            MFI         PDF */
170 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
171 #define DP_MFD_850	(48 - 1)
172 #define DP_MFN_850	41
173 
174 #define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
175 #define DP_MFD_800	(3 - 1)
176 #define DP_MFN_800	1
177 
178 #define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
179 #define DP_MFD_700	(24 - 1)
180 #define DP_MFN_700	7
181 
182 #define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
183 #define DP_MFD_665	(96 - 1)
184 #define DP_MFN_665	89
185 
186 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
187 #define DP_MFD_532	(24 - 1)
188 #define DP_MFN_532	13
189 
190 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
191 #define DP_MFD_400	(3 - 1)
192 #define DP_MFN_400	1
193 
194 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
195 #define DP_MFD_216	(4 - 1)
196 #define DP_MFN_216	3
197 
198 #define CHIP_REV_1_0            0x10
199 #define CHIP_REV_1_1            0x11
200 #define CHIP_REV_2_0            0x20
201 #define CHIP_REV_2_5		0x25
202 #define CHIP_REV_3_0            0x30
203 
204 #define BOARD_REV_1_0           0x0
205 #define BOARD_REV_2_0           0x1
206 
207 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
208 #include <asm/types.h>
209 
210 #define __REG(x)	(*((volatile u32 *)(x)))
211 #define __REG16(x)	(*((volatile u16 *)(x)))
212 #define __REG8(x)	(*((volatile u8 *)(x)))
213 
214 struct clkctl {
215 	u32	ccr;
216 	u32	ccdr;
217 	u32	csr;
218 	u32	ccsr;
219 	u32	cacrr;
220 	u32	cbcdr;
221 	u32	cbcmr;
222 	u32	cscmr1;
223 	u32	cscmr2;
224 	u32	cscdr1;
225 	u32	cs1cdr;
226 	u32	cs2cdr;
227 	u32	cdcdr;
228 	u32	chsccdr;
229 	u32	cscdr2;
230 	u32	cscdr3;
231 	u32	cscdr4;
232 	u32	cwdr;
233 	u32	cdhipr;
234 	u32	cdcr;
235 	u32	ctor;
236 	u32	clpcr;
237 	u32	cisr;
238 	u32	cimr;
239 	u32	ccosr;
240 	u32	cgpr;
241 	u32	ccgr0;
242 	u32	ccgr1;
243 	u32	ccgr2;
244 	u32	ccgr3;
245 	u32	ccgr4;
246 	u32	ccgr5;
247 	u32	ccgr6;
248 	u32	cmeor;
249 };
250 
251 /* WEIM registers */
252 struct weim {
253 	u32	csgcr1;
254 	u32	csgcr2;
255 	u32	csrcr1;
256 	u32	csrcr2;
257 	u32	cswcr1;
258 	u32	cswcr2;
259 };
260 
261 /* GPIO Registers */
262 struct gpio_regs {
263 	u32	gpio_dr;
264 	u32	gpio_dir;
265 	u32	gpio_psr;
266 };
267 
268 /* System Reset Controller (SRC) */
269 struct src {
270 	u32	scr;
271 	u32	sbmr;
272 	u32	srsr;
273 	u32	reserved1[2];
274 	u32	sisr;
275 	u32	simr;
276 };
277 #endif /* __ASSEMBLER__*/
278 
279 #endif				/*  __ASM_ARCH_MXC_MX51_H__ */
280