1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
24 #define __ASM_ARCH_MX5_IMX_REGS_H__
25 
26 #if defined(CONFIG_MX51)
27 #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
28 #define IPU_SOC_BASE_ADDR	0x40000000
29 #define IPU_SOC_OFFSET		0x1E000000
30 #define SPBA0_BASE_ADDR         0x70000000
31 #define AIPS1_BASE_ADDR         0x73F00000
32 #define AIPS2_BASE_ADDR         0x83F00000
33 #define CSD0_BASE_ADDR          0x90000000
34 #define CSD1_BASE_ADDR          0xA0000000
35 #define NFC_BASE_ADDR_AXI       0xCFFF0000
36 #define CS1_BASE_ADDR           0xB8000000
37 #elif defined(CONFIG_MX53)
38 #define IPU_SOC_BASE_ADDR	0x18000000
39 #define IPU_SOC_OFFSET		0x06000000
40 #define SPBA0_BASE_ADDR         0x50000000
41 #define AIPS1_BASE_ADDR         0x53F00000
42 #define AIPS2_BASE_ADDR         0x63F00000
43 #define CSD0_BASE_ADDR          0x70000000
44 #define CSD1_BASE_ADDR          0xB0000000
45 #define NFC_BASE_ADDR_AXI       0xF7FF0000
46 #define IRAM_BASE_ADDR          0xF8000000
47 #define CS1_BASE_ADDR           0xF4000000
48 #define SATA_BASE_ADDR		0x10000000
49 #else
50 #error "CPU_TYPE not defined"
51 #endif
52 
53 #define IRAM_SIZE		0x00020000	/* 128 KB */
54 
55 /*
56  * SPBA global module enabled #0
57  */
58 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
59 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
60 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
61 #define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
62 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
63 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
64 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
65 #define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
66 #define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
67 #define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
68 #define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
69 #define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
70 
71 /*
72  * AIPS 1
73  */
74 #define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
75 #define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
76 #define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
77 #define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
78 #define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
79 #define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
80 #define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
81 #define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
82 #define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
83 #define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
84 #define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
85 #define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
86 #define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
87 #define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
88 #define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
89 #define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
90 #define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
91 #define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
92 #define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
93 #define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
94 
95 #if defined(CONFIG_MX53)
96 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
97 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
98 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
99 #define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
100 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
101 #endif
102 /*
103  * AIPS 2
104  */
105 #define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
106 #define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
107 #define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
108 #ifdef	CONFIG_MX53
109 #define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
110 #endif
111 #define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
112 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
113 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
114 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
115 #define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
116 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
117 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
118 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
119 #define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
120 #define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
121 #define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
122 #define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
123 #define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
124 #define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
125 #define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
126 #define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
127 #define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
128 #define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
129 #define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
130 #define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
131 #define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
132 #define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
133 #define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
134 #define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
135 #define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
136 #define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
137 #define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
138 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
139 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
140 
141 #if defined(CONFIG_MX53)
142 #define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
143 #endif
144 
145 /*
146  * WEIM CSnGCR1
147  */
148 #define CSEN		1
149 #define SWR		(1 << 1)
150 #define SRD		(1 << 2)
151 #define MUM		(1 << 3)
152 #define WFL		(1 << 4)
153 #define RFL		(1 << 5)
154 #define CRE		(1 << 6)
155 #define CREP		(1 << 7)
156 #define BL(x)		(((x) & 0x7) << 8)
157 #define WC		(1 << 11)
158 #define BCD(x)		(((x) & 0x3) << 12)
159 #define BCS(x)		(((x) & 0x3) << 14)
160 #define DSZ(x)		(((x) & 0x7) << 16)
161 #define SP		(1 << 19)
162 #define CSREC(x)	(((x) & 0x7) << 20)
163 #define AUS		(1 << 23)
164 #define GBC(x)		(((x) & 0x7) << 24)
165 #define WP		(1 << 27)
166 #define PSZ(x)		(((x) & 0x0f << 28)
167 
168 /*
169  * WEIM CSnGCR2
170  */
171 #define ADH(x)		(((x) & 0x3))
172 #define DAPS(x)		(((x) & 0x0f << 4)
173 #define DAE		(1 << 8)
174 #define DAP		(1 << 9)
175 #define MUX16_BYP	(1 << 12)
176 
177 /*
178  * WEIM CSnRCR1
179  */
180 #define RCSN(x)		(((x) & 0x7))
181 #define RCSA(x)		(((x) & 0x7) << 4)
182 #define OEN(x)		(((x) & 0x7) << 8)
183 #define OEA(x)		(((x) & 0x7) << 12)
184 #define RADVN(x)	(((x) & 0x7) << 16)
185 #define RAL		(1 << 19)
186 #define RADVA(x)	(((x) & 0x7) << 20)
187 #define RWSC(x)		(((x) & 0x3f) << 24)
188 
189 /*
190  * WEIM CSnRCR2
191  */
192 #define RBEN(x)		(((x) & 0x7))
193 #define RBE		(1 << 3)
194 #define RBEA(x)		(((x) & 0x7) << 4)
195 #define RL(x)		(((x) & 0x3) << 8)
196 #define PAT(x)		(((x) & 0x7) << 12)
197 #define APR		(1 << 15)
198 
199 /*
200  * WEIM CSnWCR1
201  */
202 #define WCSN(x)		(((x) & 0x7))
203 #define WCSA(x)		(((x) & 0x7) << 3)
204 #define WEN(x)		(((x) & 0x7) << 6)
205 #define WEA(x)		(((x) & 0x7) << 9)
206 #define WBEN(x)		(((x) & 0x7) << 12)
207 #define WBEA(x)		(((x) & 0x7) << 15)
208 #define WADVN(x)	(((x) & 0x7) << 18)
209 #define WADVA(x)	(((x) & 0x7) << 21)
210 #define WWSC(x)		(((x) & 0x3f) << 24)
211 #define WBED1		(1 << 30)
212 #define WAL		(1 << 31)
213 
214 /*
215  * WEIM CSnWCR2
216  */
217 #define WBED		1
218 
219 /*
220  * WEIM WCR
221  */
222 #define BCM		1
223 #define GBCD(x)		(((x) & 0x3) << 1)
224 #define INTEN		(1 << 4)
225 #define INTPOL		(1 << 5)
226 #define WDOG_EN		(1 << 8)
227 #define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
228 
229 #define CS0_128					0
230 #define CS0_64M_CS1_64M				1
231 #define CS0_64M_CS1_32M_CS2_32M			2
232 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
233 
234 /*
235  * CSPI register definitions
236  */
237 #define MXC_ECSPI
238 #define MXC_CSPICTRL_EN		(1 << 0)
239 #define MXC_CSPICTRL_MODE	(1 << 1)
240 #define MXC_CSPICTRL_XCH	(1 << 2)
241 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
242 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
243 #define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
244 #define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
245 #define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
246 #define MXC_CSPICTRL_MAXBITS	0xfff
247 #define MXC_CSPICTRL_TC		(1 << 7)
248 #define MXC_CSPICTRL_RXOVF	(1 << 6)
249 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
250 #define MAX_SPI_BYTES	32
251 
252 /* Bit position inside CTRL register to be associated with SS */
253 #define MXC_CSPICTRL_CHAN	18
254 
255 /* Bit position inside CON register to be associated with SS */
256 #define MXC_CSPICON_POL		4
257 #define MXC_CSPICON_PHA		0
258 #define MXC_CSPICON_SSPOL	12
259 #define MXC_SPI_BASE_ADDRESSES \
260 	CSPI1_BASE_ADDR, \
261 	CSPI2_BASE_ADDR, \
262 	CSPI3_BASE_ADDR,
263 
264 /*
265  * Number of GPIO pins per port
266  */
267 #define GPIO_NUM_PIN            32
268 
269 #define IIM_SREV	0x24
270 #define ROM_SI_REV	0x48
271 
272 #define NFC_BUF_SIZE	0x1000
273 
274 /* M4IF */
275 #define M4IF_FBPM0	0x40
276 #define M4IF_FIDBP	0x48
277 
278 /* Assuming 24MHz input clock with doubler ON */
279 /*                            MFI         PDF */
280 #define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
281 #define DP_MFD_864	(180 - 1) /* PL Dither mode */
282 #define DP_MFN_864	180
283 #define DP_MFN_800_DIT	60 /* PL Dither mode */
284 
285 #define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
286 #define DP_MFD_850	(48 - 1)
287 #define DP_MFN_850	41
288 
289 #define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
290 #define DP_MFD_800	(3 - 1)
291 #define DP_MFN_800	1
292 
293 #define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
294 #define DP_MFD_700	(24 - 1)
295 #define DP_MFN_700	7
296 
297 #define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
298 #define DP_MFD_665	(96 - 1)
299 #define DP_MFN_665	89
300 
301 #define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
302 #define DP_MFD_532	(24 - 1)
303 #define DP_MFN_532	13
304 
305 #define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
306 #define DP_MFD_400	(3 - 1)
307 #define DP_MFN_400	1
308 
309 #define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
310 #define DP_MFD_216	(4 - 1)
311 #define DP_MFN_216	3
312 
313 #define CHIP_REV_1_0            0x10
314 #define CHIP_REV_1_1            0x11
315 #define CHIP_REV_2_0            0x20
316 #define CHIP_REV_2_5		0x25
317 #define CHIP_REV_3_0            0x30
318 
319 #define BOARD_REV_1_0           0x0
320 #define BOARD_REV_2_0           0x1
321 
322 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
323 
324 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
325 #include <asm/types.h>
326 
327 #define __REG(x)	(*((volatile u32 *)(x)))
328 #define __REG16(x)	(*((volatile u16 *)(x)))
329 #define __REG8(x)	(*((volatile u8 *)(x)))
330 
331 struct clkctl {
332 	u32	ccr;
333 	u32	ccdr;
334 	u32	csr;
335 	u32	ccsr;
336 	u32	cacrr;
337 	u32	cbcdr;
338 	u32	cbcmr;
339 	u32	cscmr1;
340 	u32	cscmr2;
341 	u32	cscdr1;
342 	u32	cs1cdr;
343 	u32	cs2cdr;
344 	u32	cdcdr;
345 	u32	chsccdr;
346 	u32	cscdr2;
347 	u32	cscdr3;
348 	u32	cscdr4;
349 	u32	cwdr;
350 	u32	cdhipr;
351 	u32	cdcr;
352 	u32	ctor;
353 	u32	clpcr;
354 	u32	cisr;
355 	u32	cimr;
356 	u32	ccosr;
357 	u32	cgpr;
358 	u32	ccgr0;
359 	u32	ccgr1;
360 	u32	ccgr2;
361 	u32	ccgr3;
362 	u32	ccgr4;
363 	u32	ccgr5;
364 	u32	ccgr6;
365 #if defined(CONFIG_MX53)
366 	u32	ccgr7;
367 #endif
368 	u32	cmeor;
369 };
370 
371 /* DPLL registers */
372 struct dpll {
373 	u32	dp_ctl;
374 	u32	dp_config;
375 	u32	dp_op;
376 	u32	dp_mfd;
377 	u32	dp_mfn;
378 	u32	dp_mfn_minus;
379 	u32	dp_mfn_plus;
380 	u32	dp_hfs_op;
381 	u32	dp_hfs_mfd;
382 	u32	dp_hfs_mfn;
383 	u32	dp_mfn_togc;
384 	u32	dp_destat;
385 };
386 /* WEIM registers */
387 struct weim {
388 	u32	cs0gcr1;
389 	u32	cs0gcr2;
390 	u32	cs0rcr1;
391 	u32	cs0rcr2;
392 	u32	cs0wcr1;
393 	u32	cs0wcr2;
394 	u32	cs1gcr1;
395 	u32	cs1gcr2;
396 	u32	cs1rcr1;
397 	u32	cs1rcr2;
398 	u32	cs1wcr1;
399 	u32	cs1wcr2;
400 	u32	cs2gcr1;
401 	u32	cs2gcr2;
402 	u32	cs2rcr1;
403 	u32	cs2rcr2;
404 	u32	cs2wcr1;
405 	u32	cs2wcr2;
406 	u32	cs3gcr1;
407 	u32	cs3gcr2;
408 	u32	cs3rcr1;
409 	u32	cs3rcr2;
410 	u32	cs3wcr1;
411 	u32	cs3wcr2;
412 	u32	cs4gcr1;
413 	u32	cs4gcr2;
414 	u32	cs4rcr1;
415 	u32	cs4rcr2;
416 	u32	cs4wcr1;
417 	u32	cs4wcr2;
418 	u32	cs5gcr1;
419 	u32	cs5gcr2;
420 	u32	cs5rcr1;
421 	u32	cs5rcr2;
422 	u32	cs5wcr1;
423 	u32	cs5wcr2;
424 	u32	wcr;
425 	u32	wiar;
426 	u32	ear;
427 };
428 
429 #if defined(CONFIG_MX51)
430 struct iomuxc {
431 	u32	gpr0;
432 	u32	gpr1;
433 	u32	omux0;
434 	u32	omux1;
435 	u32	omux2;
436 	u32	omux3;
437 	u32	omux4;
438 };
439 #elif defined(CONFIG_MX53)
440 struct iomuxc {
441 	u32	gpr0;
442 	u32	gpr1;
443 	u32	gpr2;
444 	u32	omux0;
445 	u32	omux1;
446 	u32	omux2;
447 	u32	omux3;
448 	u32	omux4;
449 };
450 #endif
451 
452 /* System Reset Controller (SRC) */
453 struct src {
454 	u32	scr;
455 	u32	sbmr;
456 	u32	srsr;
457 	u32	reserved1[2];
458 	u32	sisr;
459 	u32	simr;
460 };
461 
462 struct srtc_regs {
463 	u32	lpscmr;		/* 0x00 */
464 	u32	lpsclr;		/* 0x04 */
465 	u32	lpsar;		/* 0x08 */
466 	u32	lpsmcr;		/* 0x0c */
467 	u32	lpcr;		/* 0x10 */
468 	u32	lpsr;		/* 0x14 */
469 	u32	lppdr;		/* 0x18 */
470 	u32	lpgr;		/* 0x1c */
471 	u32	hpcmr;		/* 0x20 */
472 	u32	hpclr;		/* 0x24 */
473 	u32	hpamr;		/* 0x28 */
474 	u32	hpalr;		/* 0x2c */
475 	u32	hpcr;		/* 0x30 */
476 	u32	hpisr;		/* 0x34 */
477 	u32	hpienr;		/* 0x38 */
478 };
479 
480 /* CSPI registers */
481 struct cspi_regs {
482 	u32 rxdata;
483 	u32 txdata;
484 	u32 ctrl;
485 	u32 cfg;
486 	u32 intr;
487 	u32 dma;
488 	u32 stat;
489 	u32 period;
490 };
491 
492 struct iim_regs {
493 	u32	stat;
494 	u32	statm;
495 	u32     err;
496 	u32	emask;
497 	u32	fctl;
498 	u32	ua;
499 	u32	la;
500 	u32	sdat;
501 	u32	prev;
502 	u32	srev;
503 	u32	preg_p;
504 	u32	scs0;
505 	u32	scs1;
506 	u32	scs2;
507 	u32	scs3;
508 	u32	res0[0x1f1];
509 	struct fuse_bank {
510 		u32	fuse_regs[0x20];
511 		u32	fuse_rsvd[0xe0];
512 	} bank[4];
513 };
514 
515 struct fuse_bank0_regs {
516 	u32	fuse0_23[24];
517 	u32	gp[8];
518 };
519 
520 struct fuse_bank1_regs {
521 	u32	fuse0_8[9];
522 	u32	mac_addr[6];
523 	u32	fuse15_31[0x11];
524 };
525 
526 #endif /* __ASSEMBLER__*/
527 
528 #endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
529