1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_MX5_IMX_REGS_H__ 8 #define __ASM_ARCH_MX5_IMX_REGS_H__ 9 10 #define ARCH_MXC 11 12 #define CONFIG_SYS_CACHELINE_SIZE 64 13 14 #if defined(CONFIG_MX51) 15 #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 16 #define IPU_SOC_BASE_ADDR 0x40000000 17 #define IPU_SOC_OFFSET 0x1E000000 18 #define SPBA0_BASE_ADDR 0x70000000 19 #define AIPS1_BASE_ADDR 0x73F00000 20 #define AIPS2_BASE_ADDR 0x83F00000 21 #define CSD0_BASE_ADDR 0x90000000 22 #define CSD1_BASE_ADDR 0xA0000000 23 #define NFC_BASE_ADDR_AXI 0xCFFF0000 24 #define CS1_BASE_ADDR 0xB8000000 25 #elif defined(CONFIG_MX53) 26 #define IPU_SOC_BASE_ADDR 0x18000000 27 #define IPU_SOC_OFFSET 0x06000000 28 #define SPBA0_BASE_ADDR 0x50000000 29 #define AIPS1_BASE_ADDR 0x53F00000 30 #define AIPS2_BASE_ADDR 0x63F00000 31 #define CSD0_BASE_ADDR 0x70000000 32 #define CSD1_BASE_ADDR 0xB0000000 33 #define NFC_BASE_ADDR_AXI 0xF7FF0000 34 #define IRAM_BASE_ADDR 0xF8000000 35 #define CS1_BASE_ADDR 0xF4000000 36 #define SATA_BASE_ADDR 0x10000000 37 #else 38 #error "CPU_TYPE not defined" 39 #endif 40 41 #define IRAM_SIZE 0x00020000 /* 128 KB */ 42 43 /* 44 * SPBA global module enabled #0 45 */ 46 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 47 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 48 #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) 49 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 50 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 51 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 52 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 53 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 54 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 55 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 56 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 57 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 58 59 /* 60 * AIPS 1 61 */ 62 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 63 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 64 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 65 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 66 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 67 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 68 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 69 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 70 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 71 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 72 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 73 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 74 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 75 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 76 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 77 #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000) 78 #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000) 79 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 80 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 81 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 82 83 #if defined(CONFIG_MX53) 84 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) 85 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) 86 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) 87 #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) 88 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) 89 #endif 90 /* 91 * AIPS 2 92 */ 93 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 94 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 95 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 96 #ifdef CONFIG_MX53 97 #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) 98 #endif 99 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 100 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 101 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 102 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 103 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 104 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 105 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 106 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 107 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 108 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 109 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 110 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 111 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 112 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 113 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 114 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 115 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 116 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 117 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 118 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 119 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 120 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 121 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 122 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 123 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 124 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 125 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 126 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 127 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 128 129 #if defined(CONFIG_MX53) 130 #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) 131 #endif 132 133 /* 134 * WEIM CSnGCR1 135 */ 136 #define CSEN 1 137 #define SWR (1 << 1) 138 #define SRD (1 << 2) 139 #define MUM (1 << 3) 140 #define WFL (1 << 4) 141 #define RFL (1 << 5) 142 #define CRE (1 << 6) 143 #define CREP (1 << 7) 144 #define BL(x) (((x) & 0x7) << 8) 145 #define WC (1 << 11) 146 #define BCD(x) (((x) & 0x3) << 12) 147 #define BCS(x) (((x) & 0x3) << 14) 148 #define DSZ(x) (((x) & 0x7) << 16) 149 #define SP (1 << 19) 150 #define CSREC(x) (((x) & 0x7) << 20) 151 #define AUS (1 << 23) 152 #define GBC(x) (((x) & 0x7) << 24) 153 #define WP (1 << 27) 154 #define PSZ(x) (((x) & 0x0f << 28) 155 156 /* 157 * WEIM CSnGCR2 158 */ 159 #define ADH(x) (((x) & 0x3)) 160 #define DAPS(x) (((x) & 0x0f << 4) 161 #define DAE (1 << 8) 162 #define DAP (1 << 9) 163 #define MUX16_BYP (1 << 12) 164 165 /* 166 * WEIM CSnRCR1 167 */ 168 #define RCSN(x) (((x) & 0x7)) 169 #define RCSA(x) (((x) & 0x7) << 4) 170 #define OEN(x) (((x) & 0x7) << 8) 171 #define OEA(x) (((x) & 0x7) << 12) 172 #define RADVN(x) (((x) & 0x7) << 16) 173 #define RAL (1 << 19) 174 #define RADVA(x) (((x) & 0x7) << 20) 175 #define RWSC(x) (((x) & 0x3f) << 24) 176 177 /* 178 * WEIM CSnRCR2 179 */ 180 #define RBEN(x) (((x) & 0x7)) 181 #define RBE (1 << 3) 182 #define RBEA(x) (((x) & 0x7) << 4) 183 #define RL(x) (((x) & 0x3) << 8) 184 #define PAT(x) (((x) & 0x7) << 12) 185 #define APR (1 << 15) 186 187 /* 188 * WEIM CSnWCR1 189 */ 190 #define WCSN(x) (((x) & 0x7)) 191 #define WCSA(x) (((x) & 0x7) << 3) 192 #define WEN(x) (((x) & 0x7) << 6) 193 #define WEA(x) (((x) & 0x7) << 9) 194 #define WBEN(x) (((x) & 0x7) << 12) 195 #define WBEA(x) (((x) & 0x7) << 15) 196 #define WADVN(x) (((x) & 0x7) << 18) 197 #define WADVA(x) (((x) & 0x7) << 21) 198 #define WWSC(x) (((x) & 0x3f) << 24) 199 #define WBED1 (1 << 30) 200 #define WAL (1 << 31) 201 202 /* 203 * WEIM CSnWCR2 204 */ 205 #define WBED 1 206 207 /* 208 * CSPI register definitions 209 */ 210 #define MXC_ECSPI 211 #define MXC_CSPICTRL_EN (1 << 0) 212 #define MXC_CSPICTRL_MODE (1 << 1) 213 #define MXC_CSPICTRL_XCH (1 << 2) 214 #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 215 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 216 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 217 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 218 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 219 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 220 #define MXC_CSPICTRL_MAXBITS 0xfff 221 #define MXC_CSPICTRL_TC (1 << 7) 222 #define MXC_CSPICTRL_RXOVF (1 << 6) 223 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 224 #define MAX_SPI_BYTES 32 225 226 /* Bit position inside CTRL register to be associated with SS */ 227 #define MXC_CSPICTRL_CHAN 18 228 229 /* Bit position inside CON register to be associated with SS */ 230 #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 231 #define MXC_CSPICON_POL 4 /* SCLK polarity */ 232 #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 233 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 234 #define MXC_SPI_BASE_ADDRESSES \ 235 CSPI1_BASE_ADDR, \ 236 CSPI2_BASE_ADDR, \ 237 CSPI3_BASE_ADDR, 238 239 /* 240 * Number of GPIO pins per port 241 */ 242 #define GPIO_NUM_PIN 32 243 244 #define IIM_SREV 0x24 245 #define ROM_SI_REV 0x48 246 247 #define NFC_BUF_SIZE 0x1000 248 249 /* M4IF */ 250 #define M4IF_FBPM0 0x40 251 #define M4IF_FIDBP 0x48 252 #define M4IF_GENP_WEIM_MM_MASK 0x00000001 253 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 254 255 /* Assuming 24MHz input clock with doubler ON */ 256 /* MFI PDF */ 257 #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0)) 258 #define DP_MFD_864 (180 - 1) /* PL Dither mode */ 259 #define DP_MFN_864 180 260 #define DP_MFN_800_DIT 60 /* PL Dither mode */ 261 262 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 263 #define DP_MFD_850 (48 - 1) 264 #define DP_MFN_850 41 265 266 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 267 #define DP_MFD_800 (3 - 1) 268 #define DP_MFN_800 1 269 270 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 271 #define DP_MFD_700 (24 - 1) 272 #define DP_MFN_700 7 273 274 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 275 #define DP_MFD_665 (96 - 1) 276 #define DP_MFN_665 89 277 278 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 279 #define DP_MFD_532 (24 - 1) 280 #define DP_MFN_532 13 281 282 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 283 #define DP_MFD_400 (3 - 1) 284 #define DP_MFN_400 1 285 286 #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) 287 #define DP_MFD_455 (48 - 1) 288 #define DP_MFN_455 23 289 290 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 291 #define DP_MFD_216 (4 - 1) 292 #define DP_MFN_216 3 293 294 #define CHIP_REV_1_0 0x10 295 #define CHIP_REV_1_1 0x11 296 #define CHIP_REV_2_0 0x20 297 #define CHIP_REV_2_5 0x25 298 #define CHIP_REV_3_0 0x30 299 300 #define BOARD_REV_1_0 0x0 301 #define BOARD_REV_2_0 0x1 302 303 #define BOARD_VER_OFFSET 0x8 304 305 #define IMX_IIM_BASE (IIM_BASE_ADDR) 306 307 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 308 #include <asm/types.h> 309 310 #define __REG(x) (*((volatile u32 *)(x))) 311 #define __REG16(x) (*((volatile u16 *)(x))) 312 #define __REG8(x) (*((volatile u8 *)(x))) 313 314 struct clkctl { 315 u32 ccr; 316 u32 ccdr; 317 u32 csr; 318 u32 ccsr; 319 u32 cacrr; 320 u32 cbcdr; 321 u32 cbcmr; 322 u32 cscmr1; 323 u32 cscmr2; 324 u32 cscdr1; 325 u32 cs1cdr; 326 u32 cs2cdr; 327 u32 cdcdr; 328 u32 chsccdr; 329 u32 cscdr2; 330 u32 cscdr3; 331 u32 cscdr4; 332 u32 cwdr; 333 u32 cdhipr; 334 u32 cdcr; 335 u32 ctor; 336 u32 clpcr; 337 u32 cisr; 338 u32 cimr; 339 u32 ccosr; 340 u32 cgpr; 341 u32 ccgr0; 342 u32 ccgr1; 343 u32 ccgr2; 344 u32 ccgr3; 345 u32 ccgr4; 346 u32 ccgr5; 347 u32 ccgr6; 348 #if defined(CONFIG_MX53) 349 u32 ccgr7; 350 #endif 351 u32 cmeor; 352 }; 353 354 /* DPLL registers */ 355 struct dpll { 356 u32 dp_ctl; 357 u32 dp_config; 358 u32 dp_op; 359 u32 dp_mfd; 360 u32 dp_mfn; 361 u32 dp_mfn_minus; 362 u32 dp_mfn_plus; 363 u32 dp_hfs_op; 364 u32 dp_hfs_mfd; 365 u32 dp_hfs_mfn; 366 u32 dp_mfn_togc; 367 u32 dp_destat; 368 }; 369 /* WEIM registers */ 370 struct weim { 371 u32 cs0gcr1; 372 u32 cs0gcr2; 373 u32 cs0rcr1; 374 u32 cs0rcr2; 375 u32 cs0wcr1; 376 u32 cs0wcr2; 377 u32 cs1gcr1; 378 u32 cs1gcr2; 379 u32 cs1rcr1; 380 u32 cs1rcr2; 381 u32 cs1wcr1; 382 u32 cs1wcr2; 383 u32 cs2gcr1; 384 u32 cs2gcr2; 385 u32 cs2rcr1; 386 u32 cs2rcr2; 387 u32 cs2wcr1; 388 u32 cs2wcr2; 389 u32 cs3gcr1; 390 u32 cs3gcr2; 391 u32 cs3rcr1; 392 u32 cs3rcr2; 393 u32 cs3wcr1; 394 u32 cs3wcr2; 395 u32 cs4gcr1; 396 u32 cs4gcr2; 397 u32 cs4rcr1; 398 u32 cs4rcr2; 399 u32 cs4wcr1; 400 u32 cs4wcr2; 401 u32 cs5gcr1; 402 u32 cs5gcr2; 403 u32 cs5rcr1; 404 u32 cs5rcr2; 405 u32 cs5wcr1; 406 u32 cs5wcr2; 407 u32 wcr; 408 u32 wiar; 409 u32 ear; 410 }; 411 412 #if defined(CONFIG_MX51) 413 struct iomuxc { 414 u32 gpr[2]; 415 u32 omux0; 416 u32 omux1; 417 u32 omux2; 418 u32 omux3; 419 u32 omux4; 420 }; 421 #elif defined(CONFIG_MX53) 422 struct iomuxc { 423 u32 gpr[3]; 424 u32 omux0; 425 u32 omux1; 426 u32 omux2; 427 u32 omux3; 428 u32 omux4; 429 }; 430 #endif 431 432 /* System Reset Controller (SRC) */ 433 struct src { 434 u32 scr; 435 u32 sbmr; 436 u32 srsr; 437 u32 reserved1[2]; 438 u32 sisr; 439 u32 simr; 440 }; 441 442 struct srtc_regs { 443 u32 lpscmr; /* 0x00 */ 444 u32 lpsclr; /* 0x04 */ 445 u32 lpsar; /* 0x08 */ 446 u32 lpsmcr; /* 0x0c */ 447 u32 lpcr; /* 0x10 */ 448 u32 lpsr; /* 0x14 */ 449 u32 lppdr; /* 0x18 */ 450 u32 lpgr; /* 0x1c */ 451 u32 hpcmr; /* 0x20 */ 452 u32 hpclr; /* 0x24 */ 453 u32 hpamr; /* 0x28 */ 454 u32 hpalr; /* 0x2c */ 455 u32 hpcr; /* 0x30 */ 456 u32 hpisr; /* 0x34 */ 457 u32 hpienr; /* 0x38 */ 458 }; 459 460 /* CSPI registers */ 461 struct cspi_regs { 462 u32 rxdata; 463 u32 txdata; 464 u32 ctrl; 465 u32 cfg; 466 u32 intr; 467 u32 dma; 468 u32 stat; 469 u32 period; 470 }; 471 472 struct iim_regs { 473 u32 stat; 474 u32 statm; 475 u32 err; 476 u32 emask; 477 u32 fctl; 478 u32 ua; 479 u32 la; 480 u32 sdat; 481 u32 prev; 482 u32 srev; 483 u32 prg_p; 484 u32 scs0; 485 u32 scs1; 486 u32 scs2; 487 u32 scs3; 488 u32 res0[0x1f1]; 489 struct fuse_bank { 490 u32 fuse_regs[0x20]; 491 u32 fuse_rsvd[0xe0]; 492 #if defined(CONFIG_MX51) 493 } bank[4]; 494 #elif defined(CONFIG_MX53) 495 } bank[5]; 496 #endif 497 }; 498 499 struct fuse_bank0_regs { 500 u32 fuse0_7[8]; 501 u32 uid[8]; 502 u32 fuse16_23[8]; 503 #if defined(CONFIG_MX51) 504 u32 imei[8]; 505 #elif defined(CONFIG_MX53) 506 u32 gp[8]; 507 #endif 508 }; 509 510 struct fuse_bank1_regs { 511 u32 fuse0_8[9]; 512 u32 mac_addr[6]; 513 u32 fuse15_31[0x11]; 514 }; 515 516 #if defined(CONFIG_MX53) 517 struct fuse_bank4_regs { 518 u32 fuse0_4[5]; 519 u32 gp[3]; 520 u32 fuse8_31[0x18]; 521 }; 522 #endif 523 524 #endif /* __ASSEMBLER__*/ 525 526 #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ 527