1 /*
2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
8 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
9 
10 #define MXC_CCM_BASE	CCM_BASE_ADDR
11 
12 /* DPLL register mapping structure */
13 struct mxc_pll_reg {
14 	u32 ctrl;
15 	u32 config;
16 	u32 op;
17 	u32 mfd;
18 	u32 mfn;
19 	u32 mfn_minus;
20 	u32 mfn_plus;
21 	u32 hfs_op;
22 	u32 hfs_mfd;
23 	u32 hfs_mfn;
24 	u32 mfn_togc;
25 	u32 destat;
26 };
27 
28 /* Register maping of CCM*/
29 struct mxc_ccm_reg {
30 	u32 ccr;	/* 0x0000 */
31 	u32 ccdr;
32 	u32 csr;
33 	u32 ccsr;
34 	u32 cacrr;	/* 0x0010*/
35 	u32 cbcdr;
36 	u32 cbcmr;
37 	u32 cscmr1;
38 	u32 cscmr2;	/* 0x0020 */
39 	u32 cscdr1;
40 	u32 cs1cdr;
41 	u32 cs2cdr;
42 	u32 cdcdr;	/* 0x0030 */
43 	u32 chscdr;
44 	u32 cscdr2;
45 	u32 cscdr3;
46 	u32 cscdr4;	/* 0x0040 */
47 	u32 cwdr;
48 	u32 cdhipr;
49 	u32 cdcr;
50 	u32 ctor;	/* 0x0050 */
51 	u32 clpcr;
52 	u32 cisr;
53 	u32 cimr;
54 	u32 ccosr;	/* 0x0060 */
55 	u32 cgpr;
56 	u32 CCGR0;
57 	u32 CCGR1;
58 	u32 CCGR2;	/* 0x0070 */
59 	u32 CCGR3;
60 	u32 CCGR4;
61 	u32 CCGR5;
62 	u32 CCGR6;	/* 0x0080 */
63 #ifdef CONFIG_MX53
64 	u32 CCGR7;      /* 0x0084 */
65 #endif
66 	u32 cmeor;
67 };
68 
69 /* Define the bits in register CCR */
70 #define MXC_CCM_CCR_COSC_EN			(0x1 << 12)
71 #if defined(CONFIG_MX51)
72 #define MXC_CCM_CCR_FPM_MULT			(0x1 << 11)
73 #endif
74 #define MXC_CCM_CCR_CAMP2_EN			(0x1 << 10)
75 #define MXC_CCM_CCR_CAMP1_EN			(0x1 << 9)
76 #if defined(CONFIG_MX51)
77 #define MXC_CCM_CCR_FPM_EN			(0x1 << 8)
78 #endif
79 #define MXC_CCM_CCR_OSCNT_OFFSET		0
80 #define MXC_CCM_CCR_OSCNT_MASK			0xFF
81 #define MXC_CCM_CCR_OSCNT(v)			((v) & 0xFF)
82 #define MXC_CCM_CCR_OSCNT_RD(r)			((r) & 0xFF)
83 
84 /* Define the bits in register CCSR */
85 #if defined(CONFIG_MX51)
86 #define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
87 #elif defined(CONFIG_MX53)
88 #define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
89 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
90 #endif
91 #define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
92 #define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
93 #define MXC_CCM_CCSR_STEP_SEL(v)		(((v) & 0x3) << 7)
94 #define MXC_CCM_CCSR_STEP_SEL_RD(r)		(((r) >> 7) & 0x3)
95 #define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
97 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v)		(((v) & 0x3) << 5)
98 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r)	(((r) >> 5) & 0x3)
99 #define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
101 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v)		(((v) & 0x3) << 3)
102 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r)	(((r) >> 3) & 0x3)
103 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
104 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
105 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
106 
107 /* Define the bits in register CACRR */
108 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
109 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
110 #define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
111 #define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
112 
113 /* Define the bits in register CBCDR */
114 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
115 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
116 #define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
117 #define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
118 #define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
119 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
120 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
121 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
122 #define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
123 #define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
124 #define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
125 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
126 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
127 #define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
128 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
129 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
130 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
131 #define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
132 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
133 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
134 #define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
135 #define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
136 #define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
137 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
138 #define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
139 #define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
140 #define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
141 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
142 #define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
143 #define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
144 #define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
145 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
146 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
147 #define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
148 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
149 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
150 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
151 #define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
152 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
153 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
154 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
155 #define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
156 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
157 
158 /* Define the bits in register CSCMR1 */
159 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
160 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
161 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
162 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
163 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
164 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
165 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
166 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
167 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
168 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
169 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
170 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
171 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
172 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
173 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
174 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
175 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
176 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
177 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
178 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
179 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
180 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
181 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
182 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
183 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
184 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
185 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
186 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
187 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
188 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
189 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
190 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
191 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
192 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
193 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
194 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
195 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
196 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
197 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
198 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
199 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
200 #define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
201 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
202 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
203 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
204 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
205 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
206 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
207 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
208 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
209 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
210 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
211 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
212 
213 /* Define the bits in register CSCDR2 */
214 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
215 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
216 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
217 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
218 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
219 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
220 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
221 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
222 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
223 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
224 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
225 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
226 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
227 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
228 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
229 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
230 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
231 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
232 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
233 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
234 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
235 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
236 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
237 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
238 
239 /* Define the bits in register CBCMR */
240 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
241 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
242 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
243 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
244 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
245 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
246 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
247 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
248 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
249 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
250 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
251 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
252 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
253 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
254 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
255 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
256 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
257 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
258 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
259 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
260 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
261 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
262 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
263 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
264 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
265 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
266 
267 /* Define the bits in register CSCDR1 */
268 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
269 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
270 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
271 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
272 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
273 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
274 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
275 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
276 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
277 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
278 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
279 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
280 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
281 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
282 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
283 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
284 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
285 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
286 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
287 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
288 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
289 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
290 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
291 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
292 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
293 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
294 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
295 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
296 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
297 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
298 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
299 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
300 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
301 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
302 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
303 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
304 
305 /* Define the bits in register CCDR */
306 #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
307 
308 /* Define the bits in register CCGRx */
309 #define MXC_CCM_CCGR_CG_MASK				0x3
310 #define MXC_CCM_CCGR_CG_OFF				0x0
311 #define MXC_CCM_CCGR_CG_RUN_ON				0x1
312 #define MXC_CCM_CCGR_CG_ON				0x3
313 
314 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
315 #define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
316 #define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
317 #define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
318 #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
319 #define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
320 #define MXC_CCM_CCGR0_TZIC_OFFSET			6
321 #define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
322 #define MXC_CCM_CCGR0_DAP_OFFSET			8
323 #define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
324 #define MXC_CCM_CCGR0_TPIU_OFFSET			10
325 #define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
326 #define MXC_CCM_CCGR0_CTI2_OFFSET			12
327 #define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
328 #define MXC_CCM_CCGR0_CTI3_OFFSET			14
329 #define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
330 #define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
331 #define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
332 #define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
333 #define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
334 #define MXC_CCM_CCGR0_ROMCP_OFFSET			20
335 #define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
336 #define MXC_CCM_CCGR0_ROM_OFFSET			22
337 #define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
338 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
339 #define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
340 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
341 #define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
342 #define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
343 #define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
344 #define MXC_CCM_CCGR0_IIM_OFFSET			30
345 #define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
346 
347 #define MXC_CCM_CCGR1_TMAX1_OFFSET			0
348 #define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
349 #define MXC_CCM_CCGR1_TMAX2_OFFSET			2
350 #define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
351 #define MXC_CCM_CCGR1_TMAX3_OFFSET			4
352 #define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
353 #define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
354 #define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
355 #define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
356 #define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
357 #define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
358 #define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
359 #define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
360 #define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
361 #define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
362 #define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
363 #define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
364 #define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
365 #define MXC_CCM_CCGR1_I2C1_OFFSET			18
366 #define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
367 #define MXC_CCM_CCGR1_I2C2_OFFSET			20
368 #define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
369 #if defined(CONFIG_MX51)
370 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
371 #define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
372 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
373 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
374 #elif defined(CONFIG_MX53)
375 #define MXC_CCM_CCGR1_I2C3_OFFSET			22
376 #define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
377 #endif
378 #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
379 #define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
380 #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
381 #define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
382 #define MXC_CCM_CCGR1_SCC_OFFSET			30
383 #define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
384 
385 #if defined(CONFIG_MX51)
386 #define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
387 #define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
388 #endif
389 #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
390 #define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
391 #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
392 #define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
393 #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
394 #define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
395 #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
396 #define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
397 #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
398 #define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
399 #define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
400 #define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
401 #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
402 #define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
403 #define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
404 #define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
405 #define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
406 #define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
407 #define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
408 #define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
409 #define MXC_CCM_CCGR2_OWIRE_OFFSET			22
410 #define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
411 #define MXC_CCM_CCGR2_FEC_OFFSET			24
412 #define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
413 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
414 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
415 #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
416 #define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
417 #define MXC_CCM_CCGR2_TVE_OFFSET			30
418 #define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
419 
420 #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
421 #define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
422 #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
423 #define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
424 #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
425 #define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
426 #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
427 #define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
428 #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
429 #define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
430 #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
431 #define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
432 #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
433 #define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
434 #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
435 #define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
436 #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
437 #define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
438 #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
439 #define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
440 #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
441 #define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
442 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
443 #define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
444 #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
445 #define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
446 #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
447 #define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
448 #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
449 #define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
450 #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
451 #define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
452 
453 #define MXC_CCM_CCGR4_PATA_OFFSET			0
454 #define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
455 #if defined(CONFIG_MX51)
456 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
457 #define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
458 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
459 #define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
460 #elif defined(CONFIG_MX53)
461 #define MXC_CCM_CCGR4_SATA_OFFSET			2
462 #define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
463 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
464 #define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
465 #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
466 #define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
467 #define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
468 #define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
469 #define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
470 #define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
471 #endif
472 #define MXC_CCM_CCGR4_SAHARA_OFFSET			14
473 #define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
474 #define MXC_CCM_CCGR4_RTIC_OFFSET			16
475 #define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
476 #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
477 #define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
478 #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
479 #define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
480 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
481 #define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
482 #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
483 #define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
484 #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
485 #define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
486 #define MXC_CCM_CCGR4_SRTC_OFFSET			28
487 #define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
488 #define MXC_CCM_CCGR4_SDMA_OFFSET			30
489 #define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
490 
491 #define MXC_CCM_CCGR5_SPBA_OFFSET			0
492 #define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
493 #define MXC_CCM_CCGR5_GPU_OFFSET			2
494 #define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
495 #define MXC_CCM_CCGR5_GARB_OFFSET			4
496 #define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
497 #define MXC_CCM_CCGR5_VPU_OFFSET			6
498 #define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
499 #define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
500 #define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
501 #define MXC_CCM_CCGR5_IPU_OFFSET			10
502 #define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
503 #if defined(CONFIG_MX51)
504 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
505 #define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
506 #elif defined(CONFIG_MX53)
507 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
508 #define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
509 #endif
510 #define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
511 #define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
512 #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
513 #define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
514 #define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
515 #define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
516 #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
517 #define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
518 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
519 #define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
520 #define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
521 #define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
522 #define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
523 #define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
524 #if defined(CONFIG_MX51)
525 #define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
526 #define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
527 #endif
528 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
529 #define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
530 
531 #if defined(CONFIG_MX53)
532 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
533 #define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
534 #define MXC_CCM_CCGR6_OCRAM_OFFSET			2
535 #define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
536 #endif
537 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
538 #define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
539 #if defined(CONFIG_MX51)
540 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
541 #define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
542 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
543 #define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
544 #elif defined(CONFIG_MX53)
545 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
546 #define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
547 #endif
548 #define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
549 #define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
550 #define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
551 #define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
552 #define MXC_CCM_CCGR6_GPU2D_OFFSET			14
553 #define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
554 #if defined(CONFIG_MX53)
555 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
556 #define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
557 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
558 #define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
559 #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
560 #define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
561 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
562 #define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
563 #define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
564 #define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
565 #define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
566 #define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
567 #define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
568 #define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
569 #define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
570 #define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
571 
572 #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
573 #define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
574 #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
575 #define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
576 #define MXC_CCM_CCGR7_MLB_OFFSET			4
577 #define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
578 #define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
579 #define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
580 #define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
581 #define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
582 #define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
583 #define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
584 #define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
585 #define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
586 #define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
587 #define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
588 #endif
589 
590 /* Define the bits in register CLPCR */
591 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
592 
593 #define	MXC_DPLLC_CTL_HFSM				(1 << 7)
594 #define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
595 
596 #define	MXC_DPLLC_OP_PDF_MASK				0xf
597 #define	MXC_DPLLC_OP_MFI_OFFSET				4
598 #define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
599 #define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
600 #define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
601 
602 #define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff
603 
604 #define	MXC_DPLLC_MFN_MFN_MASK				0x7ffffff
605 
606 #endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
607