1/* 2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <asm/arch/imx-regs.h> 10#include <generated/asm-offsets.h> 11#include <asm/macro.h> 12 13/* 14 * AIPS setup - Only setup MPROTx registers. 15 * The PACR default values are good. 16 * 17 * Default argument values: 18 * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to 19 * user-mode. 20 * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for 21 * SDMA to access them. 22 */ 23.macro init_aips mpr=0x77777777, opacr=0x00000000 24 ldr r0, =AIPS1_BASE_ADDR 25 ldr r1, =\mpr 26 str r1, [r0, #AIPS_MPR_0_7] 27 str r1, [r0, #AIPS_MPR_8_15] 28 ldr r2, =AIPS2_BASE_ADDR 29 str r1, [r2, #AIPS_MPR_0_7] 30 str r1, [r2, #AIPS_MPR_8_15] 31 32 /* Did not change the AIPS control registers access type. */ 33 ldr r1, =\opacr 34 str r1, [r0, #AIPS_OPACR_0_7] 35 str r1, [r0, #AIPS_OPACR_8_15] 36 str r1, [r0, #AIPS_OPACR_16_23] 37 str r1, [r0, #AIPS_OPACR_24_31] 38 str r1, [r0, #AIPS_OPACR_32_39] 39 str r1, [r2, #AIPS_OPACR_0_7] 40 str r1, [r2, #AIPS_OPACR_8_15] 41 str r1, [r2, #AIPS_OPACR_16_23] 42 str r1, [r2, #AIPS_OPACR_24_31] 43 str r1, [r2, #AIPS_OPACR_32_39] 44.endm 45 46/* 47 * MAX (Multi-Layer AHB Crossbar Switch) setup 48 * 49 * Default argument values: 50 * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 51 * - SGPCR: always park on last master 52 * - MGPCR: restore default values 53 */ 54.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 55 ldr r0, =MAX_BASE_ADDR 56 ldr r1, =\mpr 57 str r1, [r0, #MAX_MPR0] /* for S0 */ 58 str r1, [r0, #MAX_MPR1] /* for S1 */ 59 str r1, [r0, #MAX_MPR2] /* for S2 */ 60 str r1, [r0, #MAX_MPR3] /* for S3 */ 61 str r1, [r0, #MAX_MPR4] /* for S4 */ 62 ldr r1, =\sgpcr 63 str r1, [r0, #MAX_SGPCR0] /* for S0 */ 64 str r1, [r0, #MAX_SGPCR1] /* for S1 */ 65 str r1, [r0, #MAX_SGPCR2] /* for S2 */ 66 str r1, [r0, #MAX_SGPCR3] /* for S3 */ 67 str r1, [r0, #MAX_SGPCR4] /* for S4 */ 68 ldr r1, =\mgpcr 69 str r1, [r0, #MAX_MGPCR0] /* for M0 */ 70 str r1, [r0, #MAX_MGPCR1] /* for M1 */ 71 str r1, [r0, #MAX_MGPCR2] /* for M2 */ 72 str r1, [r0, #MAX_MGPCR3] /* for M3 */ 73 str r1, [r0, #MAX_MGPCR4] /* for M4 */ 74 str r1, [r0, #MAX_MGPCR5] /* for M5 */ 75.endm 76 77/* 78 * M3IF setup 79 * 80 * Default argument values: 81 * - CTL: 82 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 83 * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 84 * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 85 * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 86 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 87 * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 88 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 89 * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 90 * ------------ 91 * 0x00000040 92 */ 93.macro init_m3if ctl=0x00000040 94 /* M3IF Control Register (M3IFCTL) */ 95 write32 M3IF_BASE_ADDR, \ctl 96.endm 97 98.macro core_init 99 mrc p15, 0, r1, c1, c0, 0 100 101 /* Set branch prediction enable */ 102 mrc p15, 0, r0, c1, c0, 1 103 orr r0, r0, #7 104 mcr p15, 0, r0, c1, c0, 1 105 orr r1, r1, #1 << 11 106 107 /* Set unaligned access enable */ 108 orr r1, r1, #1 << 22 109 110 /* Set low int latency enable */ 111 orr r1, r1, #1 << 21 112 113 mcr p15, 0, r1, c1, c0, 0 114 115 mov r0, #0 116 117 mcr p15, 0, r0, c15, c2, 4 118 119 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ 120 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ 121 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ 122 123 /* Setup the Peripheral Port Memory Remap Register */ 124 ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ 125 mcr p15, 0, r0, c15, c2, 4 126.endm 127