1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 4 * 5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 6 */ 7 8#include <asm/arch/imx-regs.h> 9#include <generated/asm-offsets.h> 10#include <asm/macro.h> 11 12/* 13 * AIPS setup - Only setup MPROTx registers. 14 * The PACR default values are good. 15 * 16 * Default argument values: 17 * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to 18 * user-mode. 19 * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for 20 * SDMA to access them. 21 */ 22.macro init_aips mpr=0x77777777, opacr=0x00000000 23 ldr r0, =AIPS1_BASE_ADDR 24 ldr r1, =\mpr 25 str r1, [r0, #AIPS_MPR_0_7] 26 str r1, [r0, #AIPS_MPR_8_15] 27 ldr r2, =AIPS2_BASE_ADDR 28 str r1, [r2, #AIPS_MPR_0_7] 29 str r1, [r2, #AIPS_MPR_8_15] 30 31 /* Did not change the AIPS control registers access type. */ 32 ldr r1, =\opacr 33 str r1, [r0, #AIPS_OPACR_0_7] 34 str r1, [r0, #AIPS_OPACR_8_15] 35 str r1, [r0, #AIPS_OPACR_16_23] 36 str r1, [r0, #AIPS_OPACR_24_31] 37 str r1, [r0, #AIPS_OPACR_32_39] 38 str r1, [r2, #AIPS_OPACR_0_7] 39 str r1, [r2, #AIPS_OPACR_8_15] 40 str r1, [r2, #AIPS_OPACR_16_23] 41 str r1, [r2, #AIPS_OPACR_24_31] 42 str r1, [r2, #AIPS_OPACR_32_39] 43.endm 44 45/* 46 * MAX (Multi-Layer AHB Crossbar Switch) setup 47 * 48 * Default argument values: 49 * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 50 * - SGPCR: always park on last master 51 * - MGPCR: restore default values 52 */ 53.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 54 ldr r0, =MAX_BASE_ADDR 55 ldr r1, =\mpr 56 str r1, [r0, #MAX_MPR0] /* for S0 */ 57 str r1, [r0, #MAX_MPR1] /* for S1 */ 58 str r1, [r0, #MAX_MPR2] /* for S2 */ 59 str r1, [r0, #MAX_MPR3] /* for S3 */ 60 str r1, [r0, #MAX_MPR4] /* for S4 */ 61 ldr r1, =\sgpcr 62 str r1, [r0, #MAX_SGPCR0] /* for S0 */ 63 str r1, [r0, #MAX_SGPCR1] /* for S1 */ 64 str r1, [r0, #MAX_SGPCR2] /* for S2 */ 65 str r1, [r0, #MAX_SGPCR3] /* for S3 */ 66 str r1, [r0, #MAX_SGPCR4] /* for S4 */ 67 ldr r1, =\mgpcr 68 str r1, [r0, #MAX_MGPCR0] /* for M0 */ 69 str r1, [r0, #MAX_MGPCR1] /* for M1 */ 70 str r1, [r0, #MAX_MGPCR2] /* for M2 */ 71 str r1, [r0, #MAX_MGPCR3] /* for M3 */ 72 str r1, [r0, #MAX_MGPCR4] /* for M4 */ 73 str r1, [r0, #MAX_MGPCR5] /* for M5 */ 74.endm 75 76/* 77 * M3IF setup 78 * 79 * Default argument values: 80 * - CTL: 81 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 82 * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 83 * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 84 * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 85 * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 86 * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 87 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 88 * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 89 * ------------ 90 * 0x00000040 91 */ 92.macro init_m3if ctl=0x00000040 93 /* M3IF Control Register (M3IFCTL) */ 94 write32 M3IF_BASE_ADDR, \ctl 95.endm 96 97.macro core_init 98 mrc p15, 0, r1, c1, c0, 0 99 100 /* Set branch prediction enable */ 101 mrc p15, 0, r0, c1, c0, 1 102 orr r0, r0, #7 103 mcr p15, 0, r0, c1, c0, 1 104 orr r1, r1, #1 << 11 105 106 /* Set unaligned access enable */ 107 orr r1, r1, #1 << 22 108 109 /* Set low int latency enable */ 110 orr r1, r1, #1 << 21 111 112 mcr p15, 0, r1, c1, c0, 0 113 114 mov r0, #0 115 116 mcr p15, 0, r0, c15, c2, 4 117 118 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ 119 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ 120 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ 121 122 /* Setup the Peripheral Port Memory Remap Register */ 123 ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ 124 mcr p15, 0, r0, c15, c2, 4 125.endm 126