1/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22/*
23 * AIPS setup - Only setup MPROTx registers.
24 * The PACR default values are good.
25 */
26.macro init_aips
27	/*
28	 * Set all MPROTx to be non-bufferable, trusted for R/W,
29	 * not forced to user-mode.
30	 */
31	ldr r0, =AIPS1_BASE_ADDR
32	ldr r1, =AIPS_MPR_CONFIG
33	str r1, [r0, #0x00]
34	str r1, [r0, #0x04]
35	ldr r0, =AIPS2_BASE_ADDR
36	str r1, [r0, #0x00]
37	str r1, [r0, #0x04]
38
39	/*
40	 * Clear the on and off peripheral modules Supervisor Protect bit
41	 * for SDMA to access them. Did not change the AIPS control registers
42	 * (offset 0x20) access type
43	 */
44	ldr r0, =AIPS1_BASE_ADDR
45	ldr r1, =AIPS_OPACR_CONFIG
46	str r1, [r0, #0x40]
47	str r1, [r0, #0x44]
48	str r1, [r0, #0x48]
49	str r1, [r0, #0x4C]
50	str r1, [r0, #0x50]
51	ldr r0, =AIPS2_BASE_ADDR
52	str r1, [r0, #0x40]
53	str r1, [r0, #0x44]
54	str r1, [r0, #0x48]
55	str r1, [r0, #0x4C]
56	str r1, [r0, #0x50]
57.endm
58
59/* MAX (Multi-Layer AHB Crossbar Switch) setup */
60.macro init_max
61	ldr r0, =MAX_BASE_ADDR
62	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
63	ldr r1, =MAX_MPR_CONFIG
64	str r1, [r0, #0x000]        /* for S0 */
65	str r1, [r0, #0x100]        /* for S1 */
66	str r1, [r0, #0x200]        /* for S2 */
67	str r1, [r0, #0x300]        /* for S3 */
68	str r1, [r0, #0x400]        /* for S4 */
69	/* SGPCR - always park on last master */
70	ldr r1, =MAX_SGPCR_CONFIG
71	str r1, [r0, #0x010]        /* for S0 */
72	str r1, [r0, #0x110]        /* for S1 */
73	str r1, [r0, #0x210]        /* for S2 */
74	str r1, [r0, #0x310]        /* for S3 */
75	str r1, [r0, #0x410]        /* for S4 */
76	/* MGPCR - restore default values */
77	ldr r1, =MAX_MGPCR_CONFIG
78	str r1, [r0, #0x800]        /* for M0 */
79	str r1, [r0, #0x900]        /* for M1 */
80	str r1, [r0, #0xA00]        /* for M2 */
81	str r1, [r0, #0xB00]        /* for M3 */
82	str r1, [r0, #0xC00]        /* for M4 */
83	str r1, [r0, #0xD00]        /* for M5 */
84.endm
85
86/* M3IF setup */
87.macro init_m3if
88	/* Configure M3IF registers */
89	ldr r1, =M3IF_BASE_ADDR
90	/*
91	* M3IF Control Register (M3IFCTL)
92	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
93	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
94	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
95	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
96	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
97	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
98	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
99	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
100	*						------------
101	*						  0x00000040
102	*/
103	ldr r0, =M3IF_CONFIG
104	str r0, [r1]  /* M3IF control reg */
105.endm
106
107.macro core_init
108	mrc 15, 0, r1, c1, c0, 0
109
110	mrc 15, 0, r0, c1, c0, 1
111	orr r0, r0, #7
112	mcr 15, 0, r0, c1, c0, 1
113	orr r1, r1, #(1<<11)
114
115	/* Set unaligned access enable */
116	orr r1, r1, #(1<<22)
117
118	/* Set low int latency enable */
119	orr r1, r1, #(1<<21)
120
121	mcr 15, 0, r1, c1, c0, 0
122
123	mov r0, #0
124
125	/* Set branch prediction enable */
126	mcr 15, 0, r0, c15, c2, 4
127
128	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
129	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
130	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
131
132	/*
133	 * initializes very early AIPS
134	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
135	 * M3IF
136	 * Also setup the Peripheral Port Remap register inside the core
137	 */
138	ldr r0, =0x40000015        /* start from AIPS 2GB region */
139	mcr p15, 0, r0, c15, c2, 4
140.endm
141