1 /* 2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __ASM_ARCH_MX35_H 26 #define __ASM_ARCH_MX35_H 27 28 /* 29 * IRAM 30 */ 31 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */ 32 #define IRAM_SIZE 0x00020000 /* 128 KB */ 33 34 /* 35 * AIPS 1 36 */ 37 #define AIPS1_BASE_ADDR 0x43F00000 38 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR 39 #define MAX_BASE_ADDR 0x43F04000 40 #define EVTMON_BASE_ADDR 0x43F08000 41 #define CLKCTL_BASE_ADDR 0x43F0C000 42 #define I2C1_BASE_ADDR 0x43F80000 43 #define I2C3_BASE_ADDR 0x43F84000 44 #define ATA_BASE_ADDR 0x43F8C000 45 #define UART1_BASE 0x43F90000 46 #define UART2_BASE 0x43F94000 47 #define I2C2_BASE_ADDR 0x43F98000 48 #define CSPI1_BASE_ADDR 0x43FA4000 49 #define IOMUXC_BASE_ADDR 0x43FAC000 50 51 /* 52 * SPBA 53 */ 54 #define SPBA_BASE_ADDR 0x50000000 55 #define UART3_BASE 0x5000C000 56 #define CSPI2_BASE_ADDR 0x50010000 57 #define ATA_DMA_BASE_ADDR 0x50020000 58 #define FEC_BASE_ADDR 0x50038000 59 #define SPBA_CTRL_BASE_ADDR 0x5003C000 60 61 /* 62 * AIPS 2 63 */ 64 #define AIPS2_BASE_ADDR 0x53F00000 65 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR 66 #define CCM_BASE_ADDR 0x53F80000 67 #define GPT1_BASE_ADDR 0x53F90000 68 #define EPIT1_BASE_ADDR 0x53F94000 69 #define EPIT2_BASE_ADDR 0x53F98000 70 #define GPIO3_BASE_ADDR 0x53FA4000 71 #define MMC_SDHC1_BASE_ADDR 0x53FB4000 72 #define MMC_SDHC2_BASE_ADDR 0x53FB8000 73 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 74 #define IPU_CTRL_BASE_ADDR 0x53FC0000 75 #define GPIO1_BASE_ADDR 0x53FCC000 76 #define GPIO2_BASE_ADDR 0x53FD0000 77 #define SDMA_BASE_ADDR 0x53FD4000 78 #define RTC_BASE_ADDR 0x53FD8000 79 #define WDOG_BASE_ADDR 0x53FDC000 80 #define PWM_BASE_ADDR 0x53FE0000 81 #define RTIC_BASE_ADDR 0x53FEC000 82 #define IIM_BASE_ADDR 0x53FF0000 83 84 #define IMX_CCM_BASE CCM_BASE_ADDR 85 86 /* 87 * ROMPATCH and AVIC 88 */ 89 #define ROMPATCH_BASE_ADDR 0x60000000 90 #define AVIC_BASE_ADDR 0x68000000 91 92 /* 93 * NAND, SDRAM, WEIM, M3IF, EMI controllers 94 */ 95 #define EXT_MEM_CTRL_BASE 0xB8000000 96 #define ESDCTL_BASE_ADDR 0xB8001000 97 #define WEIM_BASE_ADDR 0xB8002000 98 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR 99 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) 100 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) 101 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) 102 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) 103 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) 104 #define M3IF_BASE_ADDR 0xB8003000 105 #define EMI_BASE_ADDR 0xB8004000 106 107 #define NFC_BASE_ADDR 0xBB000000 108 109 /* 110 * Memory regions and CS 111 */ 112 #define IPU_MEM_BASE_ADDR 0x70000000 113 #define CSD0_BASE_ADDR 0x80000000 114 #define CSD1_BASE_ADDR 0x90000000 115 #define CS0_BASE_ADDR 0xA0000000 116 #define CS1_BASE_ADDR 0xA8000000 117 #define CS2_BASE_ADDR 0xB0000000 118 #define CS3_BASE_ADDR 0xB2000000 119 #define CS4_BASE_ADDR 0xB4000000 120 #define CS5_BASE_ADDR 0xB6000000 121 122 /* 123 * IRQ Controller Register Definitions. 124 */ 125 #define AVIC_NIMASK 0x04 126 #define AVIC_INTTYPEH 0x18 127 #define AVIC_INTTYPEL 0x1C 128 129 /* L210 */ 130 #define L2CC_BASE_ADDR 0x30000000 131 #define L2_CACHE_LINE_SIZE 32 132 #define L2_CACHE_CTL_REG 0x100 133 #define L2_CACHE_AUX_CTL_REG 0x104 134 #define L2_CACHE_SYNC_REG 0x730 135 #define L2_CACHE_INV_LINE_REG 0x770 136 #define L2_CACHE_INV_WAY_REG 0x77C 137 #define L2_CACHE_CLEAN_LINE_REG 0x7B0 138 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 139 #define L2_CACHE_DBG_CTL_REG 0xF40 140 141 #define CLKMODE_AUTO 0 142 #define CLKMODE_CONSUMER 1 143 144 #define PLL_PD(x) (((x) & 0xf) << 26) 145 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 146 #define PLL_MFI(x) (((x) & 0xf) << 10) 147 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 148 149 #define _PLL_BRM(x) ((x) << 31) 150 #define _PLL_PD(x) (((x) - 1) << 26) 151 #define _PLL_MFD(x) (((x) - 1) << 16) 152 #define _PLL_MFI(x) ((x) << 10) 153 #define _PLL_MFN(x) (x) 154 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ 155 (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ 156 _PLL_MFN(mfn)) 157 158 #define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) 159 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) 160 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) 161 162 #define CSCR_U(x) (WEIM_CTRL_CS#x + 0) 163 #define CSCR_L(x) (WEIM_CTRL_CS#x + 4) 164 #define CSCR_A(x) (WEIM_CTRL_CS#x + 8) 165 166 #define IIM_SREV 0x24 167 #define ROMPATCH_REV 0x40 168 169 #define IPU_CONF IPU_CTRL_BASE_ADDR 170 171 #define IPU_CONF_PXL_ENDIAN (1<<8) 172 #define IPU_CONF_DU_EN (1<<7) 173 #define IPU_CONF_DI_EN (1<<6) 174 #define IPU_CONF_ADC_EN (1<<5) 175 #define IPU_CONF_SDC_EN (1<<4) 176 #define IPU_CONF_PF_EN (1<<3) 177 #define IPU_CONF_ROT_EN (1<<2) 178 #define IPU_CONF_IC_EN (1<<1) 179 #define IPU_CONF_CSI_EN (1<<0) 180 181 /* 182 * CSPI register definitions 183 */ 184 #define MXC_CSPI 185 #define MXC_CSPICTRL_EN (1 << 0) 186 #define MXC_CSPICTRL_MODE (1 << 1) 187 #define MXC_CSPICTRL_XCH (1 << 2) 188 #define MXC_CSPICTRL_SMC (1 << 3) 189 #define MXC_CSPICTRL_POL (1 << 4) 190 #define MXC_CSPICTRL_PHA (1 << 5) 191 #define MXC_CSPICTRL_SSCTL (1 << 6) 192 #define MXC_CSPICTRL_SSPOL (1 << 7) 193 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 194 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 195 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 196 #define MXC_CSPICTRL_TC (1 << 7) 197 #define MXC_CSPICTRL_RXOVF (1 << 6) 198 #define MXC_CSPICTRL_MAXBITS 0xfff 199 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 200 #define MAX_SPI_BYTES 4 201 202 #define MXC_SPI_BASE_ADDRESSES \ 203 0x43fa4000, \ 204 0x50010000, 205 206 #define GPIO_PORT_NUM 3 207 #define GPIO_NUM_PIN 32 208 209 #define CHIP_REV_1_0 0x10 210 #define CHIP_REV_2_0 0x20 211 212 #define BOARD_REV_1_0 0x0 213 #define BOARD_REV_2_0 0x1 214 215 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 216 #include <asm/types.h> 217 218 enum mxc_main_clocks { 219 CPU_CLK, 220 AHB_CLK, 221 IPG_CLK, 222 IPG_PER_CLK, 223 NFC_CLK, 224 USB_CLK, 225 HSP_CLK, 226 }; 227 228 enum mxc_peri_clocks { 229 UART1_BAUD, 230 UART2_BAUD, 231 UART3_BAUD, 232 SSI1_BAUD, 233 SSI2_BAUD, 234 CSI_BAUD, 235 MSHC_CLK, 236 ESDHC1_CLK, 237 ESDHC2_CLK, 238 ESDHC3_CLK, 239 SPDIF_CLK, 240 SPI1_CLK, 241 SPI2_CLK, 242 }; 243 244 /* Clock Control Module (CCM) registers */ 245 struct ccm_regs { 246 u32 ccmr; /* Control */ 247 u32 pdr0; /* Post divider 0 */ 248 u32 pdr1; /* Post divider 1 */ 249 u32 pdr2; /* Post divider 2 */ 250 u32 pdr3; /* Post divider 3 */ 251 u32 pdr4; /* Post divider 4 */ 252 u32 rcsr; /* CCM Status */ 253 u32 mpctl; /* Core PLL Control */ 254 u32 ppctl; /* Peripheral PLL Control */ 255 u32 acmr; /* Audio clock mux */ 256 u32 cosr; /* Clock out source */ 257 u32 cgr0; /* Clock Gating Control 0 */ 258 u32 cgr1; /* Clock Gating Control 1 */ 259 u32 cgr2; /* Clock Gating Control 2 */ 260 u32 cgr3; /* Clock Gating Control 3 */ 261 u32 reserved; 262 u32 dcvr0; /* DPTC Comparator 0 */ 263 u32 dcvr1; /* DPTC Comparator 0 */ 264 u32 dcvr2; /* DPTC Comparator 0 */ 265 u32 dcvr3; /* DPTC Comparator 0 */ 266 u32 ltr0; /* Load Tracking 0 */ 267 u32 ltr1; /* Load Tracking 1 */ 268 u32 ltr2; /* Load Tracking 2 */ 269 u32 ltr3; /* Load Tracking 3 */ 270 u32 ltbr0; /* Load Tracking Buffer 0 */ 271 }; 272 273 /* IIM control registers */ 274 struct iim_regs { 275 u32 iim_stat; 276 u32 iim_statm; 277 u32 iim_err; 278 u32 iim_emask; 279 u32 iim_fctl; 280 u32 iim_ua; 281 u32 iim_la; 282 u32 iim_sdat; 283 u32 iim_prev; 284 u32 iim_srev; 285 u32 iim_prog_p; 286 u32 iim_scs0; 287 u32 iim_scs1; 288 u32 iim_scs2; 289 u32 iim_scs3; 290 }; 291 292 /* General Purpose Timer (GPT) registers */ 293 struct gpt_regs { 294 u32 ctrl; /* control */ 295 u32 pre; /* prescaler */ 296 u32 stat; /* status */ 297 u32 intr; /* interrupt */ 298 u32 cmp[3]; /* output compare 1-3 */ 299 u32 capt[2]; /* input capture 1-2 */ 300 u32 counter; /* counter */ 301 }; 302 303 /* CSPI registers */ 304 struct cspi_regs { 305 u32 rxdata; 306 u32 txdata; 307 u32 ctrl; 308 u32 intr; 309 u32 dma; 310 u32 stat; 311 u32 period; 312 u32 test; 313 }; 314 315 /* Watchdog Timer (WDOG) registers */ 316 struct wdog_regs { 317 u16 wcr; /* Control */ 318 u16 wsr; /* Service */ 319 u16 wrsr; /* Reset Status */ 320 u16 wicr; /* Interrupt Control */ 321 u16 wmcr; /* Misc Control */ 322 }; 323 324 struct esdc_regs { 325 u32 esdctl0; 326 u32 esdcfg0; 327 u32 esdctl1; 328 u32 esdcfg1; 329 u32 esdmisc; 330 u32 reserved[4]; 331 u32 esdcdly[5]; 332 u32 esdcdlyl; 333 }; 334 335 #define ESDC_MISC_RST (1 << 1) 336 #define ESDC_MISC_MDDR_EN (1 << 2) 337 #define ESDC_MISC_MDDR_DL_RST (1 << 3) 338 #define ESDC_MISC_DDR_EN (1 << 8) 339 #define ESDC_MISC_DDR2_EN (1 << 9) 340 341 /* 342 * NFMS bit in RCSR register for pagesize of nandflash 343 */ 344 #define NFMS_BIT 8 345 #define NFMS_NF_DWIDTH 14 346 #define NFMS_NF_PG_SZ 8 347 348 #define CCM_RCSR_NF_16BIT_SEL (1 << 14) 349 350 #endif 351 #endif /* __ASM_ARCH_MX35_H */ 352