1 /*
2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3  *
4  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #ifndef __ASM_ARCH_MX35_H
26 #define __ASM_ARCH_MX35_H
27 
28 #define ARCH_MXC
29 
30 /*
31  * IRAM
32  */
33 #define IRAM_BASE_ADDR		0x10000000	/* internal ram */
34 #define IRAM_SIZE		0x00020000	/* 128 KB */
35 
36 #define LOW_LEVEL_SRAM_STACK	0x1001E000
37 
38 /*
39  * AIPS 1
40  */
41 #define AIPS1_BASE_ADDR         0x43F00000
42 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
43 #define MAX_BASE_ADDR           0x43F04000
44 #define EVTMON_BASE_ADDR        0x43F08000
45 #define CLKCTL_BASE_ADDR        0x43F0C000
46 #define I2C1_BASE_ADDR		0x43F80000
47 #define I2C3_BASE_ADDR          0x43F84000
48 #define ATA_BASE_ADDR           0x43F8C000
49 #define UART1_BASE		0x43F90000
50 #define UART2_BASE		0x43F94000
51 #define I2C2_BASE_ADDR          0x43F98000
52 #define CSPI1_BASE_ADDR         0x43FA4000
53 #define IOMUXC_BASE_ADDR        0x43FAC000
54 
55 /*
56  * SPBA
57  */
58 #define SPBA_BASE_ADDR          0x50000000
59 #define UART3_BASE		0x5000C000
60 #define CSPI2_BASE_ADDR         0x50010000
61 #define ATA_DMA_BASE_ADDR       0x50020000
62 #define FEC_BASE_ADDR           0x50038000
63 #define SPBA_CTRL_BASE_ADDR     0x5003C000
64 
65 /*
66  * AIPS 2
67  */
68 #define AIPS2_BASE_ADDR         0x53F00000
69 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
70 #define CCM_BASE_ADDR           0x53F80000
71 #define GPT1_BASE_ADDR          0x53F90000
72 #define EPIT1_BASE_ADDR         0x53F94000
73 #define EPIT2_BASE_ADDR         0x53F98000
74 #define GPIO3_BASE_ADDR         0x53FA4000
75 #define MMC_SDHC1_BASE_ADDR	0x53FB4000
76 #define MMC_SDHC2_BASE_ADDR	0x53FB8000
77 #define MMC_SDHC3_BASE_ADDR	0x53FBC000
78 #define IPU_CTRL_BASE_ADDR	0x53FC0000
79 #define GPIO1_BASE_ADDR		0x53FCC000
80 #define GPIO2_BASE_ADDR		0x53FD0000
81 #define SDMA_BASE_ADDR		0x53FD4000
82 #define RTC_BASE_ADDR		0x53FD8000
83 #define WDOG1_BASE_ADDR		0x53FDC000
84 #define PWM_BASE_ADDR		0x53FE0000
85 #define RTIC_BASE_ADDR		0x53FEC000
86 #define IIM_BASE_ADDR		0x53FF0000
87 #define IMX_USB_BASE		0x53FF4000
88 #define IMX_USB_PORT_OFFSET	0x400
89 
90 #define IMX_CCM_BASE		CCM_BASE_ADDR
91 
92 /*
93  * ROMPATCH and AVIC
94  */
95 #define ROMPATCH_BASE_ADDR	0x60000000
96 #define AVIC_BASE_ADDR		0x68000000
97 
98 /*
99  * NAND, SDRAM, WEIM, M3IF, EMI controllers
100  */
101 #define EXT_MEM_CTRL_BASE	0xB8000000
102 #define ESDCTL_BASE_ADDR	0xB8001000
103 #define WEIM_BASE_ADDR		0xB8002000
104 #define WEIM_CTRL_CS0		WEIM_BASE_ADDR
105 #define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
106 #define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
107 #define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
108 #define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
109 #define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
110 #define M3IF_BASE_ADDR		0xB8003000
111 #define EMI_BASE_ADDR		0xB8004000
112 
113 #define NFC_BASE_ADDR		0xBB000000
114 
115 /*
116  * Memory regions and CS
117  */
118 #define IPU_MEM_BASE_ADDR	0x70000000
119 #define CSD0_BASE_ADDR		0x80000000
120 #define CSD1_BASE_ADDR		0x90000000
121 #define CS0_BASE_ADDR		0xA0000000
122 #define CS1_BASE_ADDR		0xA8000000
123 #define CS2_BASE_ADDR		0xB0000000
124 #define CS3_BASE_ADDR		0xB2000000
125 #define CS4_BASE_ADDR		0xB4000000
126 #define CS5_BASE_ADDR		0xB6000000
127 
128 /*
129  * IRQ Controller Register Definitions.
130  */
131 #define AVIC_NIMASK		0x04
132 #define AVIC_INTTYPEH		0x18
133 #define AVIC_INTTYPEL		0x1C
134 
135 /* L210 */
136 #define L2CC_BASE_ADDR		0x30000000
137 #define L2_CACHE_LINE_SIZE		32
138 #define L2_CACHE_CTL_REG		0x100
139 #define L2_CACHE_AUX_CTL_REG		0x104
140 #define L2_CACHE_SYNC_REG		0x730
141 #define L2_CACHE_INV_LINE_REG		0x770
142 #define L2_CACHE_INV_WAY_REG		0x77C
143 #define L2_CACHE_CLEAN_LINE_REG		0x7B0
144 #define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
145 #define L2_CACHE_DBG_CTL_REG		0xF40
146 
147 #define CLKMODE_AUTO		0
148 #define CLKMODE_CONSUMER	1
149 
150 #define PLL_PD(x)		(((x) & 0xf) << 26)
151 #define PLL_MFD(x)		(((x) & 0x3ff) << 16)
152 #define PLL_MFI(x)		(((x) & 0xf) << 10)
153 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
154 
155 #define _PLL_BRM(x)	((x) << 31)
156 #define _PLL_PD(x)	(((x) - 1) << 26)
157 #define _PLL_MFD(x)	(((x) - 1) << 16)
158 #define _PLL_MFI(x)	((x) << 10)
159 #define _PLL_MFN(x)	(x)
160 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
161 	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
162 	 _PLL_MFN(mfn))
163 
164 #define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
165 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
166 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
167 
168 #define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
169 #define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
170 #define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
171 
172 #define IIM_SREV	0x24
173 #define ROMPATCH_REV	0x40
174 
175 #define IPU_CONF	IPU_CTRL_BASE_ADDR
176 
177 #define IPU_CONF_PXL_ENDIAN	(1<<8)
178 #define IPU_CONF_DU_EN		(1<<7)
179 #define IPU_CONF_DI_EN		(1<<6)
180 #define IPU_CONF_ADC_EN		(1<<5)
181 #define IPU_CONF_SDC_EN		(1<<4)
182 #define IPU_CONF_PF_EN		(1<<3)
183 #define IPU_CONF_ROT_EN		(1<<2)
184 #define IPU_CONF_IC_EN		(1<<1)
185 #define IPU_CONF_CSI_EN		(1<<0)
186 
187 /*
188  * CSPI register definitions
189  */
190 #define MXC_CSPI
191 #define MXC_CSPICTRL_EN		(1 << 0)
192 #define MXC_CSPICTRL_MODE	(1 << 1)
193 #define MXC_CSPICTRL_XCH	(1 << 2)
194 #define MXC_CSPICTRL_SMC	(1 << 3)
195 #define MXC_CSPICTRL_POL	(1 << 4)
196 #define MXC_CSPICTRL_PHA	(1 << 5)
197 #define MXC_CSPICTRL_SSCTL	(1 << 6)
198 #define MXC_CSPICTRL_SSPOL	(1 << 7)
199 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
200 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
201 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
202 #define MXC_CSPICTRL_TC		(1 << 7)
203 #define MXC_CSPICTRL_RXOVF	(1 << 6)
204 #define MXC_CSPICTRL_MAXBITS	0xfff
205 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
206 #define MAX_SPI_BYTES	4
207 
208 #define MXC_SPI_BASE_ADDRESSES \
209 	0x43fa4000, \
210 	0x50010000,
211 
212 #define GPIO_PORT_NUM		3
213 #define GPIO_NUM_PIN		32
214 
215 #define CHIP_REV_1_0		0x10
216 #define CHIP_REV_2_0		0x20
217 
218 #define BOARD_REV_1_0		0x0
219 #define BOARD_REV_2_0		0x1
220 
221 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
222 #include <asm/types.h>
223 
224 /* Clock Control Module (CCM) registers */
225 struct ccm_regs {
226 	u32 ccmr;	/* Control */
227 	u32 pdr0;	/* Post divider 0 */
228 	u32 pdr1;	/* Post divider 1 */
229 	u32 pdr2;	/* Post divider 2 */
230 	u32 pdr3;	/* Post divider 3 */
231 	u32 pdr4;	/* Post divider 4 */
232 	u32 rcsr;	/* CCM Status */
233 	u32 mpctl;	/* Core PLL Control */
234 	u32 ppctl;	/* Peripheral PLL Control */
235 	u32 acmr;	/* Audio clock mux */
236 	u32 cosr;	/* Clock out source */
237 	u32 cgr0;	/* Clock Gating Control 0 */
238 	u32 cgr1;	/* Clock Gating Control 1 */
239 	u32 cgr2;	/* Clock Gating Control 2 */
240 	u32 cgr3;	/* Clock Gating Control 3 */
241 	u32 reserved;
242 	u32 dcvr0;	/* DPTC Comparator 0 */
243 	u32 dcvr1;	/* DPTC Comparator 0 */
244 	u32 dcvr2;	/* DPTC Comparator 0 */
245 	u32 dcvr3;	/* DPTC Comparator 0 */
246 	u32 ltr0;	/* Load Tracking 0 */
247 	u32 ltr1;	/* Load Tracking 1 */
248 	u32 ltr2;	/* Load Tracking 2 */
249 	u32 ltr3;	/* Load Tracking 3 */
250 	u32 ltbr0;	/* Load Tracking Buffer 0 */
251 };
252 
253 /* IIM control registers */
254 struct iim_regs {
255 	u32 iim_stat;
256 	u32 iim_statm;
257 	u32 iim_err;
258 	u32 iim_emask;
259 	u32 iim_fctl;
260 	u32 iim_ua;
261 	u32 iim_la;
262 	u32 iim_sdat;
263 	u32 iim_prev;
264 	u32 iim_srev;
265 	u32 iim_prg_p;
266 	u32 iim_scs0;
267 	u32 iim_scs1;
268 	u32 iim_scs2;
269 	u32 iim_scs3;
270 	u32 res1[0x1f1];
271 	struct fuse_bank {
272 		u32 fuse_regs[0x20];
273 		u32 fuse_rsvd[0xe0];
274 	} bank[3];
275 };
276 
277 struct fuse_bank0_regs {
278 	u32 fuse0_7[8];
279 	u32 uid[8];
280 	u32 fuse16_31[0x10];
281 };
282 
283 struct fuse_bank1_regs {
284 	u32 fuse0_21[0x16];
285 	u32 usr;
286 	u32 fuse23_31[9];
287 };
288 
289 /* General Purpose Timer (GPT) registers */
290 struct gpt_regs {
291 	u32 ctrl;	/* control */
292 	u32 pre;	/* prescaler */
293 	u32 stat;	/* status */
294 	u32 intr;	/* interrupt */
295 	u32 cmp[3];	/* output compare 1-3 */
296 	u32 capt[2];	/* input capture 1-2 */
297 	u32 counter;	/* counter */
298 };
299 
300 /* CSPI registers */
301 struct cspi_regs {
302 	u32 rxdata;
303 	u32 txdata;
304 	u32 ctrl;
305 	u32 intr;
306 	u32 dma;
307 	u32 stat;
308 	u32 period;
309 	u32 test;
310 };
311 
312 struct esdc_regs {
313 	u32	esdctl0;
314 	u32	esdcfg0;
315 	u32	esdctl1;
316 	u32	esdcfg1;
317 	u32	esdmisc;
318 	u32	reserved[4];
319 	u32	esdcdly[5];
320 	u32	esdcdlyl;
321 };
322 
323 #define ESDC_MISC_RST		(1 << 1)
324 #define ESDC_MISC_MDDR_EN	(1 << 2)
325 #define ESDC_MISC_MDDR_DL_RST	(1 << 3)
326 #define ESDC_MISC_DDR_EN	(1 << 8)
327 #define ESDC_MISC_DDR2_EN	(1 << 9)
328 
329 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
330 struct max_regs {
331 	u32 mpr0;
332 	u32 pad00[3];
333 	u32 sgpcr0;
334 	u32 pad01[59];
335 	u32 mpr1;
336 	u32 pad02[3];
337 	u32 sgpcr1;
338 	u32 pad03[59];
339 	u32 mpr2;
340 	u32 pad04[3];
341 	u32 sgpcr2;
342 	u32 pad05[59];
343 	u32 mpr3;
344 	u32 pad06[3];
345 	u32 sgpcr3;
346 	u32 pad07[59];
347 	u32 mpr4;
348 	u32 pad08[3];
349 	u32 sgpcr4;
350 	u32 pad09[251];
351 	u32 mgpcr0;
352 	u32 pad10[63];
353 	u32 mgpcr1;
354 	u32 pad11[63];
355 	u32 mgpcr2;
356 	u32 pad12[63];
357 	u32 mgpcr3;
358 	u32 pad13[63];
359 	u32 mgpcr4;
360 	u32 pad14[63];
361 	u32 mgpcr5;
362 };
363 
364 /* AHB <-> IP-Bus Interface (AIPS) */
365 struct aips_regs {
366 	u32 mpr_0_7;
367 	u32 mpr_8_15;
368 	u32 pad0[6];
369 	u32 pacr_0_7;
370 	u32 pacr_8_15;
371 	u32 pacr_16_23;
372 	u32 pacr_24_31;
373 	u32 pad1[4];
374 	u32 opacr_0_7;
375 	u32 opacr_8_15;
376 	u32 opacr_16_23;
377 	u32 opacr_24_31;
378 	u32 opacr_32_39;
379 };
380 
381 /*
382  * NFMS bit in RCSR register for pagesize of nandflash
383  */
384 #define NFMS_BIT		8
385 #define NFMS_NF_DWIDTH		14
386 #define NFMS_NF_PG_SZ		8
387 
388 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
389 
390 #endif
391 #endif /* __ASM_ARCH_MX35_H */
392