1 /* 2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __ASM_ARCH_MX35_H 26 #define __ASM_ARCH_MX35_H 27 28 /* 29 * IRAM 30 */ 31 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */ 32 #define IRAM_SIZE 0x00020000 /* 128 KB */ 33 34 /* 35 * AIPS 1 36 */ 37 #define AIPS1_BASE_ADDR 0x43F00000 38 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR 39 #define MAX_BASE_ADDR 0x43F04000 40 #define EVTMON_BASE_ADDR 0x43F08000 41 #define CLKCTL_BASE_ADDR 0x43F0C000 42 #define I2C_BASE_ADDR 0x43F80000 43 #define I2C3_BASE_ADDR 0x43F84000 44 #define ATA_BASE_ADDR 0x43F8C000 45 #define UART1_BASE_ADDR 0x43F90000 46 #define UART2_BASE_ADDR 0x43F94000 47 #define I2C2_BASE_ADDR 0x43F98000 48 #define CSPI1_BASE_ADDR 0x43FA4000 49 #define IOMUXC_BASE_ADDR 0x43FAC000 50 51 /* 52 * SPBA 53 */ 54 #define SPBA_BASE_ADDR 0x50000000 55 #define UART3_BASE_ADDR 0x5000C000 56 #define CSPI2_BASE_ADDR 0x50010000 57 #define ATA_DMA_BASE_ADDR 0x50020000 58 #define FEC_BASE_ADDR 0x50038000 59 #define SPBA_CTRL_BASE_ADDR 0x5003C000 60 61 /* 62 * AIPS 2 63 */ 64 #define AIPS2_BASE_ADDR 0x53F00000 65 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR 66 #define CCM_BASE_ADDR 0x53F80000 67 #define GPT1_BASE_ADDR 0x53F90000 68 #define EPIT1_BASE_ADDR 0x53F94000 69 #define EPIT2_BASE_ADDR 0x53F98000 70 #define GPIO3_BASE_ADDR 0x53FA4000 71 #define MMC_SDHC1_BASE_ADDR 0x53FB4000 72 #define MMC_SDHC2_BASE_ADDR 0x53FB8000 73 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 74 #define IPU_CTRL_BASE_ADDR 0x53FC0000 75 #define GPIO3_BASE_ADDR 0x53FA4000 76 #define GPIO1_BASE_ADDR 0x53FCC000 77 #define GPIO2_BASE_ADDR 0x53FD0000 78 #define SDMA_BASE_ADDR 0x53FD4000 79 #define RTC_BASE_ADDR 0x53FD8000 80 #define WDOG_BASE_ADDR 0x53FDC000 81 #define PWM_BASE_ADDR 0x53FE0000 82 #define RTIC_BASE_ADDR 0x53FEC000 83 #define IIM_BASE_ADDR 0x53FF0000 84 85 #define IMX_CCM_BASE CCM_BASE_ADDR 86 87 /* 88 * ROMPATCH and AVIC 89 */ 90 #define ROMPATCH_BASE_ADDR 0x60000000 91 #define AVIC_BASE_ADDR 0x68000000 92 93 /* 94 * NAND, SDRAM, WEIM, M3IF, EMI controllers 95 */ 96 #define EXT_MEM_CTRL_BASE 0xB8000000 97 #define ESDCTL_BASE_ADDR 0xB8001000 98 #define WEIM_BASE_ADDR 0xB8002000 99 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR 100 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) 101 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) 102 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) 103 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) 104 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) 105 #define M3IF_BASE_ADDR 0xB8003000 106 #define EMI_BASE_ADDR 0xB8004000 107 108 #define NFC_BASE_ADDR 0xBB000000 109 110 /* 111 * Memory regions and CS 112 */ 113 #define IPU_MEM_BASE_ADDR 0x70000000 114 #define CSD0_BASE_ADDR 0x80000000 115 #define CSD1_BASE_ADDR 0x90000000 116 #define CS0_BASE_ADDR 0xA0000000 117 #define CS1_BASE_ADDR 0xA8000000 118 #define CS2_BASE_ADDR 0xB0000000 119 #define CS3_BASE_ADDR 0xB2000000 120 #define CS4_BASE_ADDR 0xB4000000 121 #define CS5_BASE_ADDR 0xB6000000 122 123 /* 124 * IRQ Controller Register Definitions. 125 */ 126 #define AVIC_NIMASK 0x04 127 #define AVIC_INTTYPEH 0x18 128 #define AVIC_INTTYPEL 0x1C 129 130 /* L210 */ 131 #define L2CC_BASE_ADDR 0x30000000 132 #define L2_CACHE_LINE_SIZE 32 133 #define L2_CACHE_CTL_REG 0x100 134 #define L2_CACHE_AUX_CTL_REG 0x104 135 #define L2_CACHE_SYNC_REG 0x730 136 #define L2_CACHE_INV_LINE_REG 0x770 137 #define L2_CACHE_INV_WAY_REG 0x77C 138 #define L2_CACHE_CLEAN_LINE_REG 0x7B0 139 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 140 #define L2_CACHE_DBG_CTL_REG 0xF40 141 142 #define CLKMODE_AUTO 0 143 #define CLKMODE_CONSUMER 1 144 145 #define PLL_PD(x) (((x) & 0xf) << 26) 146 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 147 #define PLL_MFI(x) (((x) & 0xf) << 10) 148 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 149 150 #define CSCR_U(x) (WEIM_CTRL_CS#x + 0) 151 #define CSCR_L(x) (WEIM_CTRL_CS#x + 4) 152 #define CSCR_A(x) (WEIM_CTRL_CS#x + 8) 153 154 #define IIM_SREV 0x24 155 #define ROMPATCH_REV 0x40 156 157 #define IPU_CONF IPU_CTRL_BASE_ADDR 158 159 #define IPU_CONF_PXL_ENDIAN (1<<8) 160 #define IPU_CONF_DU_EN (1<<7) 161 #define IPU_CONF_DI_EN (1<<6) 162 #define IPU_CONF_ADC_EN (1<<5) 163 #define IPU_CONF_SDC_EN (1<<4) 164 #define IPU_CONF_PF_EN (1<<3) 165 #define IPU_CONF_ROT_EN (1<<2) 166 #define IPU_CONF_IC_EN (1<<1) 167 #define IPU_CONF_SCI_EN (1<<0) 168 169 #define GPIO_PORT_NUM 3 170 #define GPIO_NUM_PIN 32 171 172 #define CHIP_REV_1_0 0x10 173 #define CHIP_REV_2_0 0x20 174 175 #define BOARD_REV_1_0 0x0 176 #define BOARD_REV_2_0 0x1 177 178 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 179 #include <asm/types.h> 180 181 enum mxc_main_clocks { 182 CPU_CLK, 183 AHB_CLK, 184 IPG_CLK, 185 IPG_PER_CLK, 186 NFC_CLK, 187 USB_CLK, 188 HSP_CLK, 189 }; 190 191 enum mxc_peri_clocks { 192 UART1_BAUD, 193 UART2_BAUD, 194 UART3_BAUD, 195 SSI1_BAUD, 196 SSI2_BAUD, 197 CSI_BAUD, 198 MSHC_CLK, 199 ESDHC1_CLK, 200 ESDHC2_CLK, 201 ESDHC3_CLK, 202 SPDIF_CLK, 203 SPI1_CLK, 204 SPI2_CLK, 205 }; 206 207 /* Clock Control Module (CCM) registers */ 208 struct ccm_regs { 209 u32 ccmr; /* Control */ 210 u32 pdr0; /* Post divider 0 */ 211 u32 pdr1; /* Post divider 1 */ 212 u32 pdr2; /* Post divider 2 */ 213 u32 pdr3; /* Post divider 3 */ 214 u32 pdr4; /* Post divider 4 */ 215 u32 rcsr; /* CCM Status */ 216 u32 mpctl; /* Core PLL Control */ 217 u32 ppctl; /* Peripheral PLL Control */ 218 u32 acmr; /* Audio clock mux */ 219 u32 cosr; /* Clock out source */ 220 u32 cgr0; /* Clock Gating Control 0 */ 221 u32 cgr1; /* Clock Gating Control 1 */ 222 u32 cgr2; /* Clock Gating Control 2 */ 223 u32 cgr3; /* Clock Gating Control 3 */ 224 u32 reserved; 225 u32 dcvr0; /* DPTC Comparator 0 */ 226 u32 dcvr1; /* DPTC Comparator 0 */ 227 u32 dcvr2; /* DPTC Comparator 0 */ 228 u32 dcvr3; /* DPTC Comparator 0 */ 229 u32 ltr0; /* Load Tracking 0 */ 230 u32 ltr1; /* Load Tracking 1 */ 231 u32 ltr2; /* Load Tracking 2 */ 232 u32 ltr3; /* Load Tracking 3 */ 233 u32 ltbr0; /* Load Tracking Buffer 0 */ 234 }; 235 236 /* IIM control registers */ 237 struct iim_regs { 238 u32 iim_stat; 239 u32 iim_statm; 240 u32 iim_err; 241 u32 iim_emask; 242 u32 iim_fctl; 243 u32 iim_ua; 244 u32 iim_la; 245 u32 iim_sdat; 246 u32 iim_prev; 247 u32 iim_srev; 248 u32 iim_prog_p; 249 u32 iim_scs0; 250 u32 iim_scs1; 251 u32 iim_scs2; 252 u32 iim_scs3; 253 }; 254 255 /* General Purpose Timer (GPT) registers */ 256 struct gpt_regs { 257 u32 ctrl; /* control */ 258 u32 pre; /* prescaler */ 259 u32 stat; /* status */ 260 u32 intr; /* interrupt */ 261 u32 cmp[3]; /* output compare 1-3 */ 262 u32 capt[2]; /* input capture 1-2 */ 263 u32 counter; /* counter */ 264 }; 265 266 /* CSPI registers */ 267 struct cspi_regs { 268 u32 rxdata; 269 u32 txdata; 270 u32 ctrl; 271 u32 intr; 272 u32 dma; 273 u32 stat; 274 u32 period; 275 u32 test; 276 }; 277 278 /* Watchdog Timer (WDOG) registers */ 279 struct wdog_regs { 280 u16 wcr; /* Control */ 281 u16 wsr; /* Service */ 282 u16 wrsr; /* Reset Status */ 283 u16 wicr; /* Interrupt Control */ 284 u16 wmcr; /* Misc Control */ 285 }; 286 287 /* 288 * NFMS bit in RCSR register for pagesize of nandflash 289 */ 290 #define NFMS_BIT 8 291 #define NFMS_NF_DWIDTH 14 292 #define NFMS_NF_PG_SZ 8 293 294 #define CCM_RCSR_NF_16BIT_SEL (1 << 14) 295 296 extern unsigned int get_board_rev(void); 297 extern int is_soc_rev(int rev); 298 extern int sdhc_init(void); 299 300 #endif 301 #endif /* __ASM_ARCH_MX35_H */ 302