1 /*
2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3  *
4  * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __ASM_ARCH_MX35_H
10 #define __ASM_ARCH_MX35_H
11 
12 #define ARCH_MXC
13 
14 /*
15  * IRAM
16  */
17 #define IRAM_BASE_ADDR		0x10000000	/* internal ram */
18 #define IRAM_SIZE		0x00020000	/* 128 KB */
19 
20 #define LOW_LEVEL_SRAM_STACK	0x1001E000
21 
22 /*
23  * AIPS 1
24  */
25 #define AIPS1_BASE_ADDR         0x43F00000
26 #define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
27 #define MAX_BASE_ADDR           0x43F04000
28 #define EVTMON_BASE_ADDR        0x43F08000
29 #define CLKCTL_BASE_ADDR        0x43F0C000
30 #define I2C1_BASE_ADDR		0x43F80000
31 #define I2C3_BASE_ADDR          0x43F84000
32 #define ATA_BASE_ADDR           0x43F8C000
33 #define UART1_BASE		0x43F90000
34 #define UART2_BASE		0x43F94000
35 #define I2C2_BASE_ADDR          0x43F98000
36 #define CSPI1_BASE_ADDR         0x43FA4000
37 #define IOMUXC_BASE_ADDR        0x43FAC000
38 
39 /*
40  * SPBA
41  */
42 #define SPBA_BASE_ADDR          0x50000000
43 #define UART3_BASE		0x5000C000
44 #define CSPI2_BASE_ADDR         0x50010000
45 #define ATA_DMA_BASE_ADDR       0x50020000
46 #define FEC_BASE_ADDR           0x50038000
47 #define SPBA_CTRL_BASE_ADDR     0x5003C000
48 
49 /*
50  * AIPS 2
51  */
52 #define AIPS2_BASE_ADDR         0x53F00000
53 #define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
54 #define CCM_BASE_ADDR           0x53F80000
55 #define GPT1_BASE_ADDR          0x53F90000
56 #define EPIT1_BASE_ADDR         0x53F94000
57 #define EPIT2_BASE_ADDR         0x53F98000
58 #define GPIO3_BASE_ADDR         0x53FA4000
59 #define MMC_SDHC1_BASE_ADDR	0x53FB4000
60 #define MMC_SDHC2_BASE_ADDR	0x53FB8000
61 #define MMC_SDHC3_BASE_ADDR	0x53FBC000
62 #define IPU_CTRL_BASE_ADDR	0x53FC0000
63 #define GPIO1_BASE_ADDR		0x53FCC000
64 #define GPIO2_BASE_ADDR		0x53FD0000
65 #define SDMA_BASE_ADDR		0x53FD4000
66 #define RTC_BASE_ADDR		0x53FD8000
67 #define WDOG1_BASE_ADDR		0x53FDC000
68 #define PWM_BASE_ADDR		0x53FE0000
69 #define RTIC_BASE_ADDR		0x53FEC000
70 #define IIM_BASE_ADDR		0x53FF0000
71 #define IMX_USB_BASE		0x53FF4000
72 #define IMX_USB_PORT_OFFSET	0x400
73 
74 #define IMX_CCM_BASE		CCM_BASE_ADDR
75 
76 /*
77  * ROMPATCH and AVIC
78  */
79 #define ROMPATCH_BASE_ADDR	0x60000000
80 #define AVIC_BASE_ADDR		0x68000000
81 
82 /*
83  * NAND, SDRAM, WEIM, M3IF, EMI controllers
84  */
85 #define EXT_MEM_CTRL_BASE	0xB8000000
86 #define ESDCTL_BASE_ADDR	0xB8001000
87 #define WEIM_BASE_ADDR		0xB8002000
88 #define WEIM_CTRL_CS0		WEIM_BASE_ADDR
89 #define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
90 #define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
91 #define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
92 #define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
93 #define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
94 #define M3IF_BASE_ADDR		0xB8003000
95 #define EMI_BASE_ADDR		0xB8004000
96 
97 #define NFC_BASE_ADDR		0xBB000000
98 
99 /*
100  * Memory regions and CS
101  */
102 #define IPU_MEM_BASE_ADDR	0x70000000
103 #define CSD0_BASE_ADDR		0x80000000
104 #define CSD1_BASE_ADDR		0x90000000
105 #define CS0_BASE_ADDR		0xA0000000
106 #define CS1_BASE_ADDR		0xA8000000
107 #define CS2_BASE_ADDR		0xB0000000
108 #define CS3_BASE_ADDR		0xB2000000
109 #define CS4_BASE_ADDR		0xB4000000
110 #define CS5_BASE_ADDR		0xB6000000
111 
112 /*
113  * IRQ Controller Register Definitions.
114  */
115 #define AVIC_NIMASK		0x04
116 #define AVIC_INTTYPEH		0x18
117 #define AVIC_INTTYPEL		0x1C
118 
119 /* L210 */
120 #define L2CC_BASE_ADDR		0x30000000
121 #define L2_CACHE_LINE_SIZE		32
122 #define L2_CACHE_CTL_REG		0x100
123 #define L2_CACHE_AUX_CTL_REG		0x104
124 #define L2_CACHE_SYNC_REG		0x730
125 #define L2_CACHE_INV_LINE_REG		0x770
126 #define L2_CACHE_INV_WAY_REG		0x77C
127 #define L2_CACHE_CLEAN_LINE_REG		0x7B0
128 #define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
129 #define L2_CACHE_DBG_CTL_REG		0xF40
130 
131 #define CLKMODE_AUTO		0
132 #define CLKMODE_CONSUMER	1
133 
134 #define PLL_PD(x)		(((x) & 0xf) << 26)
135 #define PLL_MFD(x)		(((x) & 0x3ff) << 16)
136 #define PLL_MFI(x)		(((x) & 0xf) << 10)
137 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
138 
139 #define _PLL_BRM(x)	((x) << 31)
140 #define _PLL_PD(x)	(((x) - 1) << 26)
141 #define _PLL_MFD(x)	(((x) - 1) << 16)
142 #define _PLL_MFI(x)	((x) << 10)
143 #define _PLL_MFN(x)	(x)
144 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
145 	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
146 	 _PLL_MFN(mfn))
147 
148 #define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
149 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
150 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
151 
152 #define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
153 #define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
154 #define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
155 
156 #define IIM_SREV	0x24
157 #define ROMPATCH_REV	0x40
158 
159 #define IPU_CONF	IPU_CTRL_BASE_ADDR
160 
161 #define IPU_CONF_PXL_ENDIAN	(1<<8)
162 #define IPU_CONF_DU_EN		(1<<7)
163 #define IPU_CONF_DI_EN		(1<<6)
164 #define IPU_CONF_ADC_EN		(1<<5)
165 #define IPU_CONF_SDC_EN		(1<<4)
166 #define IPU_CONF_PF_EN		(1<<3)
167 #define IPU_CONF_ROT_EN		(1<<2)
168 #define IPU_CONF_IC_EN		(1<<1)
169 #define IPU_CONF_CSI_EN		(1<<0)
170 
171 /*
172  * CSPI register definitions
173  */
174 #define MXC_CSPI
175 #define MXC_CSPICTRL_EN		(1 << 0)
176 #define MXC_CSPICTRL_MODE	(1 << 1)
177 #define MXC_CSPICTRL_XCH	(1 << 2)
178 #define MXC_CSPICTRL_SMC	(1 << 3)
179 #define MXC_CSPICTRL_POL	(1 << 4)
180 #define MXC_CSPICTRL_PHA	(1 << 5)
181 #define MXC_CSPICTRL_SSCTL	(1 << 6)
182 #define MXC_CSPICTRL_SSPOL	(1 << 7)
183 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
184 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
185 #define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
186 #define MXC_CSPICTRL_TC		(1 << 7)
187 #define MXC_CSPICTRL_RXOVF	(1 << 6)
188 #define MXC_CSPICTRL_MAXBITS	0xfff
189 #define MXC_CSPIPERIOD_32KHZ	(1 << 15)
190 #define MAX_SPI_BYTES	4
191 
192 #define MXC_SPI_BASE_ADDRESSES \
193 	0x43fa4000, \
194 	0x50010000,
195 
196 #define GPIO_PORT_NUM		3
197 #define GPIO_NUM_PIN		32
198 
199 #define CHIP_REV_1_0		0x10
200 #define CHIP_REV_2_0		0x20
201 
202 #define BOARD_REV_1_0		0x0
203 #define BOARD_REV_2_0		0x1
204 
205 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
206 #include <asm/types.h>
207 
208 /* Clock Control Module (CCM) registers */
209 struct ccm_regs {
210 	u32 ccmr;	/* Control */
211 	u32 pdr0;	/* Post divider 0 */
212 	u32 pdr1;	/* Post divider 1 */
213 	u32 pdr2;	/* Post divider 2 */
214 	u32 pdr3;	/* Post divider 3 */
215 	u32 pdr4;	/* Post divider 4 */
216 	u32 rcsr;	/* CCM Status */
217 	u32 mpctl;	/* Core PLL Control */
218 	u32 ppctl;	/* Peripheral PLL Control */
219 	u32 acmr;	/* Audio clock mux */
220 	u32 cosr;	/* Clock out source */
221 	u32 cgr0;	/* Clock Gating Control 0 */
222 	u32 cgr1;	/* Clock Gating Control 1 */
223 	u32 cgr2;	/* Clock Gating Control 2 */
224 	u32 cgr3;	/* Clock Gating Control 3 */
225 	u32 reserved;
226 	u32 dcvr0;	/* DPTC Comparator 0 */
227 	u32 dcvr1;	/* DPTC Comparator 0 */
228 	u32 dcvr2;	/* DPTC Comparator 0 */
229 	u32 dcvr3;	/* DPTC Comparator 0 */
230 	u32 ltr0;	/* Load Tracking 0 */
231 	u32 ltr1;	/* Load Tracking 1 */
232 	u32 ltr2;	/* Load Tracking 2 */
233 	u32 ltr3;	/* Load Tracking 3 */
234 	u32 ltbr0;	/* Load Tracking Buffer 0 */
235 };
236 
237 /* IIM control registers */
238 struct iim_regs {
239 	u32 iim_stat;
240 	u32 iim_statm;
241 	u32 iim_err;
242 	u32 iim_emask;
243 	u32 iim_fctl;
244 	u32 iim_ua;
245 	u32 iim_la;
246 	u32 iim_sdat;
247 	u32 iim_prev;
248 	u32 iim_srev;
249 	u32 iim_prg_p;
250 	u32 iim_scs0;
251 	u32 iim_scs1;
252 	u32 iim_scs2;
253 	u32 iim_scs3;
254 	u32 res1[0x1f1];
255 	struct fuse_bank {
256 		u32 fuse_regs[0x20];
257 		u32 fuse_rsvd[0xe0];
258 	} bank[3];
259 };
260 
261 struct fuse_bank0_regs {
262 	u32 fuse0_7[8];
263 	u32 uid[8];
264 	u32 fuse16_31[0x10];
265 };
266 
267 struct fuse_bank1_regs {
268 	u32 fuse0_21[0x16];
269 	u32 usr;
270 	u32 fuse23_31[9];
271 };
272 
273 /* General Purpose Timer (GPT) registers */
274 struct gpt_regs {
275 	u32 ctrl;	/* control */
276 	u32 pre;	/* prescaler */
277 	u32 stat;	/* status */
278 	u32 intr;	/* interrupt */
279 	u32 cmp[3];	/* output compare 1-3 */
280 	u32 capt[2];	/* input capture 1-2 */
281 	u32 counter;	/* counter */
282 };
283 
284 /* CSPI registers */
285 struct cspi_regs {
286 	u32 rxdata;
287 	u32 txdata;
288 	u32 ctrl;
289 	u32 intr;
290 	u32 dma;
291 	u32 stat;
292 	u32 period;
293 	u32 test;
294 };
295 
296 struct esdc_regs {
297 	u32	esdctl0;
298 	u32	esdcfg0;
299 	u32	esdctl1;
300 	u32	esdcfg1;
301 	u32	esdmisc;
302 	u32	reserved[4];
303 	u32	esdcdly[5];
304 	u32	esdcdlyl;
305 };
306 
307 #define ESDC_MISC_RST		(1 << 1)
308 #define ESDC_MISC_MDDR_EN	(1 << 2)
309 #define ESDC_MISC_MDDR_DL_RST	(1 << 3)
310 #define ESDC_MISC_DDR_EN	(1 << 8)
311 #define ESDC_MISC_DDR2_EN	(1 << 9)
312 
313 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
314 struct max_regs {
315 	u32 mpr0;
316 	u32 pad00[3];
317 	u32 sgpcr0;
318 	u32 pad01[59];
319 	u32 mpr1;
320 	u32 pad02[3];
321 	u32 sgpcr1;
322 	u32 pad03[59];
323 	u32 mpr2;
324 	u32 pad04[3];
325 	u32 sgpcr2;
326 	u32 pad05[59];
327 	u32 mpr3;
328 	u32 pad06[3];
329 	u32 sgpcr3;
330 	u32 pad07[59];
331 	u32 mpr4;
332 	u32 pad08[3];
333 	u32 sgpcr4;
334 	u32 pad09[251];
335 	u32 mgpcr0;
336 	u32 pad10[63];
337 	u32 mgpcr1;
338 	u32 pad11[63];
339 	u32 mgpcr2;
340 	u32 pad12[63];
341 	u32 mgpcr3;
342 	u32 pad13[63];
343 	u32 mgpcr4;
344 	u32 pad14[63];
345 	u32 mgpcr5;
346 };
347 
348 /* AHB <-> IP-Bus Interface (AIPS) */
349 struct aips_regs {
350 	u32 mpr_0_7;
351 	u32 mpr_8_15;
352 	u32 pad0[6];
353 	u32 pacr_0_7;
354 	u32 pacr_8_15;
355 	u32 pacr_16_23;
356 	u32 pacr_24_31;
357 	u32 pad1[4];
358 	u32 opacr_0_7;
359 	u32 opacr_8_15;
360 	u32 opacr_16_23;
361 	u32 opacr_24_31;
362 	u32 opacr_32_39;
363 };
364 
365 /*
366  * NFMS bit in RCSR register for pagesize of nandflash
367  */
368 #define NFMS_BIT		8
369 #define NFMS_NF_DWIDTH		14
370 #define NFMS_NF_PG_SZ		8
371 
372 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
373 
374 #endif
375 #endif /* __ASM_ARCH_MX35_H */
376