1 /* 2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 3 * 4 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __ASM_ARCH_MX35_H 26 #define __ASM_ARCH_MX35_H 27 28 #define ARCH_MXC 29 30 /* 31 * IRAM 32 */ 33 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */ 34 #define IRAM_SIZE 0x00020000 /* 128 KB */ 35 36 /* 37 * AIPS 1 38 */ 39 #define AIPS1_BASE_ADDR 0x43F00000 40 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR 41 #define MAX_BASE_ADDR 0x43F04000 42 #define EVTMON_BASE_ADDR 0x43F08000 43 #define CLKCTL_BASE_ADDR 0x43F0C000 44 #define I2C1_BASE_ADDR 0x43F80000 45 #define I2C3_BASE_ADDR 0x43F84000 46 #define ATA_BASE_ADDR 0x43F8C000 47 #define UART1_BASE 0x43F90000 48 #define UART2_BASE 0x43F94000 49 #define I2C2_BASE_ADDR 0x43F98000 50 #define CSPI1_BASE_ADDR 0x43FA4000 51 #define IOMUXC_BASE_ADDR 0x43FAC000 52 53 /* 54 * SPBA 55 */ 56 #define SPBA_BASE_ADDR 0x50000000 57 #define UART3_BASE 0x5000C000 58 #define CSPI2_BASE_ADDR 0x50010000 59 #define ATA_DMA_BASE_ADDR 0x50020000 60 #define FEC_BASE_ADDR 0x50038000 61 #define SPBA_CTRL_BASE_ADDR 0x5003C000 62 63 /* 64 * AIPS 2 65 */ 66 #define AIPS2_BASE_ADDR 0x53F00000 67 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR 68 #define CCM_BASE_ADDR 0x53F80000 69 #define GPT1_BASE_ADDR 0x53F90000 70 #define EPIT1_BASE_ADDR 0x53F94000 71 #define EPIT2_BASE_ADDR 0x53F98000 72 #define GPIO3_BASE_ADDR 0x53FA4000 73 #define MMC_SDHC1_BASE_ADDR 0x53FB4000 74 #define MMC_SDHC2_BASE_ADDR 0x53FB8000 75 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 76 #define IPU_CTRL_BASE_ADDR 0x53FC0000 77 #define GPIO1_BASE_ADDR 0x53FCC000 78 #define GPIO2_BASE_ADDR 0x53FD0000 79 #define SDMA_BASE_ADDR 0x53FD4000 80 #define RTC_BASE_ADDR 0x53FD8000 81 #define WDOG_BASE_ADDR 0x53FDC000 82 #define PWM_BASE_ADDR 0x53FE0000 83 #define RTIC_BASE_ADDR 0x53FEC000 84 #define IIM_BASE_ADDR 0x53FF0000 85 86 #define IMX_CCM_BASE CCM_BASE_ADDR 87 88 /* 89 * ROMPATCH and AVIC 90 */ 91 #define ROMPATCH_BASE_ADDR 0x60000000 92 #define AVIC_BASE_ADDR 0x68000000 93 94 /* 95 * NAND, SDRAM, WEIM, M3IF, EMI controllers 96 */ 97 #define EXT_MEM_CTRL_BASE 0xB8000000 98 #define ESDCTL_BASE_ADDR 0xB8001000 99 #define WEIM_BASE_ADDR 0xB8002000 100 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR 101 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) 102 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) 103 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) 104 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) 105 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) 106 #define M3IF_BASE_ADDR 0xB8003000 107 #define EMI_BASE_ADDR 0xB8004000 108 109 #define NFC_BASE_ADDR 0xBB000000 110 111 /* 112 * Memory regions and CS 113 */ 114 #define IPU_MEM_BASE_ADDR 0x70000000 115 #define CSD0_BASE_ADDR 0x80000000 116 #define CSD1_BASE_ADDR 0x90000000 117 #define CS0_BASE_ADDR 0xA0000000 118 #define CS1_BASE_ADDR 0xA8000000 119 #define CS2_BASE_ADDR 0xB0000000 120 #define CS3_BASE_ADDR 0xB2000000 121 #define CS4_BASE_ADDR 0xB4000000 122 #define CS5_BASE_ADDR 0xB6000000 123 124 /* 125 * IRQ Controller Register Definitions. 126 */ 127 #define AVIC_NIMASK 0x04 128 #define AVIC_INTTYPEH 0x18 129 #define AVIC_INTTYPEL 0x1C 130 131 /* L210 */ 132 #define L2CC_BASE_ADDR 0x30000000 133 #define L2_CACHE_LINE_SIZE 32 134 #define L2_CACHE_CTL_REG 0x100 135 #define L2_CACHE_AUX_CTL_REG 0x104 136 #define L2_CACHE_SYNC_REG 0x730 137 #define L2_CACHE_INV_LINE_REG 0x770 138 #define L2_CACHE_INV_WAY_REG 0x77C 139 #define L2_CACHE_CLEAN_LINE_REG 0x7B0 140 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 141 #define L2_CACHE_DBG_CTL_REG 0xF40 142 143 #define CLKMODE_AUTO 0 144 #define CLKMODE_CONSUMER 1 145 146 #define PLL_PD(x) (((x) & 0xf) << 26) 147 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 148 #define PLL_MFI(x) (((x) & 0xf) << 10) 149 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 150 151 #define _PLL_BRM(x) ((x) << 31) 152 #define _PLL_PD(x) (((x) - 1) << 26) 153 #define _PLL_MFD(x) (((x) - 1) << 16) 154 #define _PLL_MFI(x) ((x) << 10) 155 #define _PLL_MFN(x) (x) 156 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ 157 (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ 158 _PLL_MFN(mfn)) 159 160 #define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) 161 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) 162 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) 163 164 #define CSCR_U(x) (WEIM_CTRL_CS#x + 0) 165 #define CSCR_L(x) (WEIM_CTRL_CS#x + 4) 166 #define CSCR_A(x) (WEIM_CTRL_CS#x + 8) 167 168 #define IIM_SREV 0x24 169 #define ROMPATCH_REV 0x40 170 171 #define IPU_CONF IPU_CTRL_BASE_ADDR 172 173 #define IPU_CONF_PXL_ENDIAN (1<<8) 174 #define IPU_CONF_DU_EN (1<<7) 175 #define IPU_CONF_DI_EN (1<<6) 176 #define IPU_CONF_ADC_EN (1<<5) 177 #define IPU_CONF_SDC_EN (1<<4) 178 #define IPU_CONF_PF_EN (1<<3) 179 #define IPU_CONF_ROT_EN (1<<2) 180 #define IPU_CONF_IC_EN (1<<1) 181 #define IPU_CONF_CSI_EN (1<<0) 182 183 /* 184 * CSPI register definitions 185 */ 186 #define MXC_CSPI 187 #define MXC_CSPICTRL_EN (1 << 0) 188 #define MXC_CSPICTRL_MODE (1 << 1) 189 #define MXC_CSPICTRL_XCH (1 << 2) 190 #define MXC_CSPICTRL_SMC (1 << 3) 191 #define MXC_CSPICTRL_POL (1 << 4) 192 #define MXC_CSPICTRL_PHA (1 << 5) 193 #define MXC_CSPICTRL_SSCTL (1 << 6) 194 #define MXC_CSPICTRL_SSPOL (1 << 7) 195 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 196 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 197 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 198 #define MXC_CSPICTRL_TC (1 << 7) 199 #define MXC_CSPICTRL_RXOVF (1 << 6) 200 #define MXC_CSPICTRL_MAXBITS 0xfff 201 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 202 #define MAX_SPI_BYTES 4 203 204 #define MXC_SPI_BASE_ADDRESSES \ 205 0x43fa4000, \ 206 0x50010000, 207 208 #define GPIO_PORT_NUM 3 209 #define GPIO_NUM_PIN 32 210 211 #define CHIP_REV_1_0 0x10 212 #define CHIP_REV_2_0 0x20 213 214 #define BOARD_REV_1_0 0x0 215 #define BOARD_REV_2_0 0x1 216 217 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 218 #include <asm/types.h> 219 220 /* Clock Control Module (CCM) registers */ 221 struct ccm_regs { 222 u32 ccmr; /* Control */ 223 u32 pdr0; /* Post divider 0 */ 224 u32 pdr1; /* Post divider 1 */ 225 u32 pdr2; /* Post divider 2 */ 226 u32 pdr3; /* Post divider 3 */ 227 u32 pdr4; /* Post divider 4 */ 228 u32 rcsr; /* CCM Status */ 229 u32 mpctl; /* Core PLL Control */ 230 u32 ppctl; /* Peripheral PLL Control */ 231 u32 acmr; /* Audio clock mux */ 232 u32 cosr; /* Clock out source */ 233 u32 cgr0; /* Clock Gating Control 0 */ 234 u32 cgr1; /* Clock Gating Control 1 */ 235 u32 cgr2; /* Clock Gating Control 2 */ 236 u32 cgr3; /* Clock Gating Control 3 */ 237 u32 reserved; 238 u32 dcvr0; /* DPTC Comparator 0 */ 239 u32 dcvr1; /* DPTC Comparator 0 */ 240 u32 dcvr2; /* DPTC Comparator 0 */ 241 u32 dcvr3; /* DPTC Comparator 0 */ 242 u32 ltr0; /* Load Tracking 0 */ 243 u32 ltr1; /* Load Tracking 1 */ 244 u32 ltr2; /* Load Tracking 2 */ 245 u32 ltr3; /* Load Tracking 3 */ 246 u32 ltbr0; /* Load Tracking Buffer 0 */ 247 }; 248 249 /* IIM control registers */ 250 struct iim_regs { 251 u32 iim_stat; 252 u32 iim_statm; 253 u32 iim_err; 254 u32 iim_emask; 255 u32 iim_fctl; 256 u32 iim_ua; 257 u32 iim_la; 258 u32 iim_sdat; 259 u32 iim_prev; 260 u32 iim_srev; 261 u32 iim_prog_p; 262 u32 iim_scs0; 263 u32 iim_scs1; 264 u32 iim_scs2; 265 u32 iim_scs3; 266 }; 267 268 /* General Purpose Timer (GPT) registers */ 269 struct gpt_regs { 270 u32 ctrl; /* control */ 271 u32 pre; /* prescaler */ 272 u32 stat; /* status */ 273 u32 intr; /* interrupt */ 274 u32 cmp[3]; /* output compare 1-3 */ 275 u32 capt[2]; /* input capture 1-2 */ 276 u32 counter; /* counter */ 277 }; 278 279 /* CSPI registers */ 280 struct cspi_regs { 281 u32 rxdata; 282 u32 txdata; 283 u32 ctrl; 284 u32 intr; 285 u32 dma; 286 u32 stat; 287 u32 period; 288 u32 test; 289 }; 290 291 /* Watchdog Timer (WDOG) registers */ 292 struct wdog_regs { 293 u16 wcr; /* Control */ 294 u16 wsr; /* Service */ 295 u16 wrsr; /* Reset Status */ 296 u16 wicr; /* Interrupt Control */ 297 u16 wmcr; /* Misc Control */ 298 }; 299 300 struct esdc_regs { 301 u32 esdctl0; 302 u32 esdcfg0; 303 u32 esdctl1; 304 u32 esdcfg1; 305 u32 esdmisc; 306 u32 reserved[4]; 307 u32 esdcdly[5]; 308 u32 esdcdlyl; 309 }; 310 311 #define ESDC_MISC_RST (1 << 1) 312 #define ESDC_MISC_MDDR_EN (1 << 2) 313 #define ESDC_MISC_MDDR_DL_RST (1 << 3) 314 #define ESDC_MISC_DDR_EN (1 << 8) 315 #define ESDC_MISC_DDR2_EN (1 << 9) 316 317 /* Multi-Layer AHB Crossbar Switch (MAX) registers */ 318 struct max_regs { 319 u32 mpr0; 320 u32 pad00[3]; 321 u32 sgpcr0; 322 u32 pad01[59]; 323 u32 mpr1; 324 u32 pad02[3]; 325 u32 sgpcr1; 326 u32 pad03[59]; 327 u32 mpr2; 328 u32 pad04[3]; 329 u32 sgpcr2; 330 u32 pad05[59]; 331 u32 mpr3; 332 u32 pad06[3]; 333 u32 sgpcr3; 334 u32 pad07[59]; 335 u32 mpr4; 336 u32 pad08[3]; 337 u32 sgpcr4; 338 u32 pad09[251]; 339 u32 mgpcr0; 340 u32 pad10[63]; 341 u32 mgpcr1; 342 u32 pad11[63]; 343 u32 mgpcr2; 344 u32 pad12[63]; 345 u32 mgpcr3; 346 u32 pad13[63]; 347 u32 mgpcr4; 348 u32 pad14[63]; 349 u32 mgpcr5; 350 }; 351 352 /* AHB <-> IP-Bus Interface (AIPS) */ 353 struct aips_regs { 354 u32 mpr_0_7; 355 u32 mpr_8_15; 356 u32 pad0[6]; 357 u32 pacr_0_7; 358 u32 pacr_8_15; 359 u32 pacr_16_23; 360 u32 pacr_24_31; 361 u32 pad1[4]; 362 u32 opacr_0_7; 363 u32 opacr_8_15; 364 u32 opacr_16_23; 365 u32 opacr_24_31; 366 u32 opacr_32_39; 367 }; 368 369 /* 370 * NFMS bit in RCSR register for pagesize of nandflash 371 */ 372 #define NFMS_BIT 8 373 #define NFMS_NF_DWIDTH 14 374 #define NFMS_NF_PG_SZ 8 375 376 #define CCM_RCSR_NF_16BIT_SEL (1 << 14) 377 378 #endif 379 #endif /* __ASM_ARCH_MX35_H */ 380