1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004-2009 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ 7 #define __CPU_ARM1136_MX35_CRM_REGS_H__ 8 9 /* Register bit definitions */ 10 #define MXC_CCM_CCMR_WFI (1 << 30) 11 #define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) 12 #define MXC_CCM_CCMR_VSTBY (1 << 28) 13 #define MXC_CCM_CCMR_WBEN (1 << 27) 14 #define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 15 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) 16 #define MXC_CCM_CCMR_ROMW_OFFSET 18 17 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) 18 #define MXC_CCM_CCMR_RAMW_OFFSET 16 19 #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) 20 #define MXC_CCM_CCMR_LPM_OFFSET 14 21 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 22 #define MXC_CCM_CCMR_UPE (1 << 9) 23 #define MXC_CCM_CCMR_MPE (1 << 3) 24 25 #define MXC_CCM_PDR0_PER_SEL (1 << 26) 26 #define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) 27 #define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 28 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) 29 #define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 30 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) 31 #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) 32 #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 33 #define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) 34 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 35 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) 36 #define MXC_CCM_PDR0_AUTO_CON 0x1 37 38 #define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 39 #define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) 40 #define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 41 #define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) 42 #define MXC_CCM_PDR1_MSHC_M_U (1 << 7) 43 44 #define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 45 #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) 46 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 47 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) 48 #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 49 #define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) 50 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 51 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) 52 #define MXC_CCM_PDR2_CSI_M_U (1 << 7) 53 #define MXC_CCM_PDR2_SSI_M_U (1 << 6) 54 #define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 55 #define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) 56 57 #define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 58 #define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) 59 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 60 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) 61 #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) 62 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 63 #define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) 64 #define MXC_CCM_PDR3_UART_M_U (1 << 14) 65 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 66 #define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) 67 #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) 68 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 69 #define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) 70 71 #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 72 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) 73 #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 74 #define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) 75 #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 76 #define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) 77 #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 78 #define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) 79 #define MXC_CCM_PDR4_USB_M_U (1 << 9) 80 81 /* Bit definitions for RCSR */ 82 #define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) 83 #define MXC_CCM_RCSR_BUS_16BIT (1 << 29) 84 #define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) 85 #define MXC_CCM_RCSR_PAGE_512 (0 << 27) 86 #define MXC_CCM_RCSR_PAGE_2K (1 << 27) 87 #define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) 88 #define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) 89 #define MXC_CCM_RCSR_SOFT_RESET (1 << 15) 90 #define MXC_CCM_RCSR_NF16B (1 << 14) 91 #define MXC_CCM_RCSR_NFC_4K (1 << 9) 92 #define MXC_CCM_RCSR_NFC_FMS (1 << 8) 93 94 /* Bit definitions for both MCU, PERIPHERAL PLL control registers */ 95 #define MXC_CCM_PCTL_BRM 0x80000000 96 #define MXC_CCM_PCTL_PD_OFFSET 26 97 #define MXC_CCM_PCTL_PD_MASK (0xF << 26) 98 #define MXC_CCM_PCTL_MFD_OFFSET 16 99 #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) 100 #define MXC_CCM_PCTL_MFI_OFFSET 10 101 #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) 102 #define MXC_CCM_PCTL_MFN_OFFSET 0 103 #define MXC_CCM_PCTL_MFN_MASK 0x3FF 104 105 /* Bit definitions for Audio clock mux register*/ 106 #define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 107 #define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) 108 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 109 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) 110 #define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 111 #define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) 112 #define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 113 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) 114 115 /* Bit definitions for Clock gating Register*/ 116 #define MXC_CCM_CGR_CG_MASK 0x3 117 #define MXC_CCM_CGR_CG_OFF 0x0 118 #define MXC_CCM_CGR_CG_RUN_ON 0x1 119 #define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 120 #define MXC_CCM_CGR_CG_ON 0x3 121 122 #define MXC_CCM_CGR0_ASRC_OFFSET 0 123 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) 124 #define MXC_CCM_CGR0_ATA_OFFSET 2 125 #define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) 126 #define MXC_CCM_CGR0_CAN1_OFFSET 6 127 #define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) 128 #define MXC_CCM_CGR0_CAN2_OFFSET 8 129 #define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) 130 #define MXC_CCM_CGR0_CSPI1_OFFSET 10 131 #define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) 132 #define MXC_CCM_CGR0_CSPI2_OFFSET 12 133 #define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) 134 #define MXC_CCM_CGR0_ECT_OFFSET 14 135 #define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) 136 #define MXC_CCM_CGR0_EDIO_OFFSET 16 137 #define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) 138 #define MXC_CCM_CGR0_EMI_OFFSET 18 139 #define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) 140 #define MXC_CCM_CGR0_EPIT1_OFFSET 20 141 #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) 142 #define MXC_CCM_CGR0_EPIT2_OFFSET 22 143 #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) 144 #define MXC_CCM_CGR0_ESAI_OFFSET 24 145 #define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) 146 #define MXC_CCM_CGR0_ESDHC1_OFFSET 26 147 #define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) 148 #define MXC_CCM_CGR0_ESDHC2_OFFSET 28 149 #define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) 150 #define MXC_CCM_CGR0_ESDHC3_OFFSET 30 151 #define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) 152 153 #define MXC_CCM_CGR1_FEC_OFFSET 0 154 #define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) 155 #define MXC_CCM_CGR1_GPIO1_OFFSET 2 156 #define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) 157 #define MXC_CCM_CGR1_GPIO2_OFFSET 4 158 #define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) 159 #define MXC_CCM_CGR1_GPIO3_OFFSET 6 160 #define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) 161 #define MXC_CCM_CGR1_GPT_OFFSET 8 162 #define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) 163 #define MXC_CCM_CGR1_I2C1_OFFSET 10 164 #define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) 165 #define MXC_CCM_CGR1_I2C2_OFFSET 12 166 #define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) 167 #define MXC_CCM_CGR1_I2C3_OFFSET 14 168 #define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) 169 #define MXC_CCM_CGR1_IOMUXC_OFFSET 16 170 #define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) 171 #define MXC_CCM_CGR1_IPU_OFFSET 18 172 #define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) 173 #define MXC_CCM_CGR1_KPP_OFFSET 20 174 #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) 175 #define MXC_CCM_CGR1_MLB_OFFSET 22 176 #define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) 177 #define MXC_CCM_CGR1_MSHC_OFFSET 24 178 #define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) 179 #define MXC_CCM_CGR1_OWIRE_OFFSET 26 180 #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) 181 #define MXC_CCM_CGR1_PWM_OFFSET 28 182 #define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) 183 #define MXC_CCM_CGR1_RNGC_OFFSET 30 184 #define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) 185 186 #define MXC_CCM_CGR2_RTC_OFFSET 0 187 #define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) 188 #define MXC_CCM_CGR2_RTIC_OFFSET 2 189 #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) 190 #define MXC_CCM_CGR2_SCC_OFFSET 4 191 #define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) 192 #define MXC_CCM_CGR2_SDMA_OFFSET 6 193 #define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) 194 #define MXC_CCM_CGR2_SPBA_OFFSET 8 195 #define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) 196 #define MXC_CCM_CGR2_SPDIF_OFFSET 10 197 #define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) 198 #define MXC_CCM_CGR2_SSI1_OFFSET 12 199 #define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) 200 #define MXC_CCM_CGR2_SSI2_OFFSET 14 201 #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) 202 #define MXC_CCM_CGR2_UART1_OFFSET 16 203 #define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) 204 #define MXC_CCM_CGR2_UART2_OFFSET 18 205 #define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) 206 #define MXC_CCM_CGR2_UART3_OFFSET 20 207 #define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) 208 #define MXC_CCM_CGR2_USBOTG_OFFSET 22 209 #define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) 210 #define MXC_CCM_CGR2_WDOG_OFFSET 24 211 #define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) 212 #define MXC_CCM_CGR2_MAX_OFFSET 26 213 #define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) 214 #define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) 215 #define MXC_CCM_CGR2_AUDMUX_OFFSET 30 216 #define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) 217 218 #define MXC_CCM_CGR3_CSI_OFFSET 0 219 #define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) 220 #define MXC_CCM_CGR3_IIM_OFFSET 2 221 #define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) 222 #define MXC_CCM_CGR3_GPU2D_OFFSET 4 223 #define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) 224 225 #define MXC_CCM_COSR_CLKOSEL_MASK 0x1F 226 #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 227 #define MXC_CCM_COSR_CLKOEN (1 << 5) 228 #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) 229 #define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) 230 #define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 231 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) 232 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 233 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) 234 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 235 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) 236 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 237 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) 238 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 239 #define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) 240 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) 241 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 242 243 #endif 244