1 /*
2  * Copyright 2004-2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 #ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
24 #define __CPU_ARM1136_MX35_CRM_REGS_H__
25 
26 /* Register bit definitions */
27 #define MXC_CCM_CCMR_WFI                        (1 << 30)
28 #define MXC_CCM_CCMR_STBY_EXIT_SRC              (1 << 29)
29 #define MXC_CCM_CCMR_VSTBY                      (1 << 28)
30 #define MXC_CCM_CCMR_WBEN                       (1 << 27)
31 #define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET        20
32 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
33 #define MXC_CCM_CCMR_ROMW_OFFSET               18
34 #define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
35 #define MXC_CCM_CCMR_RAMW_OFFSET               21
36 #define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 21)
37 #define MXC_CCM_CCMR_LPM_OFFSET                 14
38 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
39 #define MXC_CCM_CCMR_UPE                        (1 << 9)
40 #define MXC_CCM_CCMR_MPE                        (1 << 3)
41 
42 #define MXC_CCM_PDR0_PER_SEL			(1 << 26)
43 #define MXC_CCM_PDR0_IPU_HND_BYP                (1 << 23)
44 #define MXC_CCM_PDR0_HSP_PODF_OFFSET            20
45 #define MXC_CCM_PDR0_HSP_PODF_MASK              (0x3 << 20)
46 #define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET		16
47 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
48 #define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
49 #define MXC_CCM_PDR0_PER_PODF_OFFSET            12
50 #define MXC_CCM_PDR0_PER_PODF_MASK              (0xF << 12)
51 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
52 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
53 #define MXC_CCM_PDR0_AUTO_CON	                0x1
54 
55 #define MXC_CCM_PDR1_MSHC_PRDF_OFFSET           28
56 #define MXC_CCM_PDR1_MSHC_PRDF_MASK             (0x7 << 28)
57 #define MXC_CCM_PDR1_MSHC_PODF_OFFSET           22
58 #define MXC_CCM_PDR1_MSHC_PODF_MASK             (0x3F << 22)
59 #define MXC_CCM_PDR1_MSHC_M_U			(1 << 7)
60 
61 #define MXC_CCM_PDR2_SSI2_PRDF_OFFSET           27
62 #define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
63 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
64 #define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
65 #define MXC_CCM_PDR2_CSI_PRDF_OFFSET            19
66 #define MXC_CCM_PDR2_CSI_PRDF_MASK              (0x7 << 19)
67 #define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
68 #define MXC_CCM_PDR2_CSI_PODF_MASK              (0x7 << 16)
69 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
70 #define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
71 #define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
72 #define MXC_CCM_PDR2_SSI_M_U			(1 << 6)
73 #define MXC_CCM_PDR2_SSI1_PODF_OFFSET           0
74 #define MXC_CCM_PDR2_SSI1_PODF_MASK             (0x3F)
75 
76 #define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET          29
77 #define MXC_CCM_PDR3_SPDIF_PRDF_MASK            (0x7 << 29)
78 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
79 #define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
80 #define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
81 #define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET         19
82 #define MXC_CCM_PDR3_ESDHC3_PRDF_MASK           (0x7 << 19)
83 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
84 #define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x7 << 16)
85 #define MXC_CCM_PDR3_UART_M_U			(1 << 15)
86 #define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET         11
87 #define MXC_CCM_PDR3_ESDHC2_PRDF_MASK           (0x7 << 11)
88 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
89 #define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x7 << 8)
90 #define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
91 #define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET         3
92 #define MXC_CCM_PDR3_ESDHC1_PRDF_MASK           (0x7 << 3)
93 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
94 #define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x7)
95 
96 #define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
97 #define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
98 #define MXC_CCM_PDR4_USB_PRDF_OFFSET		25
99 #define MXC_CCM_PDR4_USB_PRDF_MASK		(0x7 << 25)
100 #define MXC_CCM_PDR4_USB_PODF_OFFSET		22
101 #define MXC_CCM_PDR4_USB_PODF_MASK		(0x7 << 22)
102 #define MXC_CCM_PDR4_PER0_PRDF_OFFSET		19
103 #define MXC_CCM_PDR4_PER0_PRDF_MASK		(0x7 << 19)
104 #define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
105 #define MXC_CCM_PDR4_PER0_PODF_MASK		(0x7 << 16)
106 #define MXC_CCM_PDR4_UART_PRDF_OFFSET		13
107 #define MXC_CCM_PDR4_UART_PRDF_MASK		(0x7 << 13)
108 #define MXC_CCM_PDR4_UART_PODF_OFFSET		10
109 #define MXC_CCM_PDR4_UART_PODF_MASK		(0x7 << 10)
110 #define MXC_CCM_PDR4_USB_M_U			(1 << 9)
111 
112 /* Bit definitions for RCSR */
113 #define MXC_CCM_RCSR_BUS_WIDTH			(1 << 29)
114 #define MXC_CCM_RCSR_BUS_16BIT			(1 << 29)
115 #define MXC_CCM_RCSR_PAGE_SIZE			(3 << 27)
116 #define MXC_CCM_RCSR_PAGE_512			(0 << 27)
117 #define MXC_CCM_RCSR_PAGE_2K			(1 << 27)
118 #define MXC_CCM_RCSR_PAGE_4K1			(2 << 27)
119 #define MXC_CCM_RCSR_PAGE_4K2			(3 << 27)
120 #define MXC_CCM_RCSR_SOFT_RESET			(1 << 15)
121 #define MXC_CCM_RCSR_NF16B			(1 << 14)
122 #define MXC_CCM_RCSR_NFC_4K			(1 << 9)
123 #define MXC_CCM_RCSR_NFC_FMS			(1 << 8)
124 
125 /* Bit definitions for both MCU, PERIPHERAL PLL control registers */
126 #define MXC_CCM_PCTL_BRM                        0x80000000
127 #define MXC_CCM_PCTL_PD_OFFSET                  26
128 #define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
129 #define MXC_CCM_PCTL_MFD_OFFSET                 16
130 #define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
131 #define MXC_CCM_PCTL_MFI_OFFSET                 10
132 #define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
133 #define MXC_CCM_PCTL_MFN_OFFSET                 0
134 #define MXC_CCM_PCTL_MFN_MASK                   0x3FF
135 
136 /* Bit definitions for Audio clock mux register*/
137 #define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET	12
138 #define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK		(0xF << 12)
139 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET	8
140 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK		(0xF << 8)
141 #define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET	4
142 #define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK		(0xF << 4)
143 #define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET	0
144 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
145 
146 /* Bit definitions for Clock gating Register*/
147 #define MXC_CCM_CGR0_ASRC_OFFSET		0
148 #define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
149 #define MXC_CCM_CGR0_ATA_OFFSET			2
150 #define MXC_CCM_CGR0_ATA_MASK			(0x3 << 2)
151 #define MXC_CCM_CGR0_CAN1_OFFSET		6
152 #define MXC_CCM_CGR0_CAN1_MASK			(0x3 << 6)
153 #define MXC_CCM_CGR0_CAN2_OFFSET		8
154 #define MXC_CCM_CGR0_CAN2_MASK			(0x3 << 8)
155 #define MXC_CCM_CGR0_CSPI1_OFFSET		10
156 #define MXC_CCM_CGR0_CSPI1_MASK			(0x3 << 10)
157 #define MXC_CCM_CGR0_CSPI2_OFFSET		12
158 #define MXC_CCM_CGR0_CSPI2_MASK			(0x3 << 12)
159 #define MXC_CCM_CGR0_ECT_OFFSET			14
160 #define MXC_CCM_CGR0_ECT_MASK			(0x3 << 14)
161 #define MXC_CCM_CGR0_EDIO_OFFSET		16
162 #define MXC_CCM_CGR0_EDIO_MASK			(0x3 << 16)
163 #define MXC_CCM_CGR0_EMI_OFFSET			18
164 #define MXC_CCM_CGR0_EMI_MASK			(0x3 << 18)
165 #define MXC_CCM_CGR0_EPIT1_OFFSET		20
166 #define MXC_CCM_CGR0_EPIT1_MASK			(0x3 << 20)
167 #define MXC_CCM_CGR0_EPIT2_OFFSET		22
168 #define MXC_CCM_CGR0_EPIT2_MASK			(0x3 << 22)
169 #define MXC_CCM_CGR0_ESAI_OFFSET		24
170 #define MXC_CCM_CGR0_ESAI_MASK			(0x3 << 24)
171 #define MXC_CCM_CGR0_ESDHC1_OFFSET		26
172 #define MXC_CCM_CGR0_ESDHC1_MASK		(0x3 << 26)
173 #define MXC_CCM_CGR0_ESDHC2_OFFSET		28
174 #define MXC_CCM_CGR0_ESDHC2_MASK		(0x3 << 28)
175 #define MXC_CCM_CGR0_ESDHC3_OFFSET		30
176 #define MXC_CCM_CGR0_ESDHC3_MASK		(0x3 << 30)
177 
178 #define MXC_CCM_CGR1_FEC_OFFSET			0
179 #define MXC_CCM_CGR1_FEC_MASK			(0x3 << 0)
180 #define MXC_CCM_CGR1_GPIO1_OFFSET		2
181 #define MXC_CCM_CGR1_GPIO1_MASK			(0x3 << 2)
182 #define MXC_CCM_CGR1_GPIO2_OFFSET		4
183 #define MXC_CCM_CGR1_GPIO2_MASK			(0x3 << 4)
184 #define MXC_CCM_CGR1_GPIO3_OFFSET		6
185 #define MXC_CCM_CGR1_GPIO3_MASK			(0x3 << 6)
186 #define MXC_CCM_CGR1_GPT_OFFSET			8
187 #define MXC_CCM_CGR1_GPT_MASK			(0x3 << 8)
188 #define MXC_CCM_CGR1_I2C1_OFFSET		10
189 #define MXC_CCM_CGR1_I2C1_MASK			(0x3 << 10)
190 #define MXC_CCM_CGR1_I2C2_OFFSET		12
191 #define MXC_CCM_CGR1_I2C2_MASK			(0x3 << 12)
192 #define MXC_CCM_CGR1_I2C3_OFFSET		14
193 #define MXC_CCM_CGR1_I2C3_MASK			(0x3 << 14)
194 #define MXC_CCM_CGR1_IOMUXC_OFFSET		16
195 #define MXC_CCM_CGR1_IOMUXC_MASK		(0x3 << 16)
196 #define MXC_CCM_CGR1_IPU_OFFSET			18
197 #define MXC_CCM_CGR1_IPU_MASK			(0x3 << 18)
198 #define MXC_CCM_CGR1_KPP_OFFSET			20
199 #define MXC_CCM_CGR1_KPP_MASK			(0x3 << 20)
200 #define MXC_CCM_CGR1_MLB_OFFSET			22
201 #define MXC_CCM_CGR1_MLB_MASK			(0x3 << 22)
202 #define MXC_CCM_CGR1_MSHC_OFFSET		24
203 #define MXC_CCM_CGR1_MSHC_MASK			(0x3 << 24)
204 #define MXC_CCM_CGR1_OWIRE_OFFSET		26
205 #define MXC_CCM_CGR1_OWIRE_MASK			(0x3 << 26)
206 #define MXC_CCM_CGR1_PWM_OFFSET			28
207 #define MXC_CCM_CGR1_PWM_MASK			(0x3 << 28)
208 #define MXC_CCM_CGR1_RNGC_OFFSET		30
209 #define MXC_CCM_CGR1_RNGC_MASK			(0x3 << 30)
210 
211 #define MXC_CCM_CGR2_RTC_OFFSET			0
212 #define MXC_CCM_CGR2_RTC_MASK			(0x3 << 0)
213 #define MXC_CCM_CGR2_RTIC_OFFSET		2
214 #define MXC_CCM_CGR2_RTIC_MASK			(0x3 << 2)
215 #define MXC_CCM_CGR2_SCC_OFFSET			4
216 #define MXC_CCM_CGR2_SCC_MASK			(0x3 << 4)
217 #define MXC_CCM_CGR2_SDMA_OFFSET		6
218 #define MXC_CCM_CGR2_SDMA_MASK			(0x3 << 6)
219 #define MXC_CCM_CGR2_SPBA_OFFSET		8
220 #define MXC_CCM_CGR2_SPBA_MASK			(0x3 << 8)
221 #define MXC_CCM_CGR2_SPDIF_OFFSET		10
222 #define MXC_CCM_CGR2_SPDIF_MASK			(0x3 << 10)
223 #define MXC_CCM_CGR2_SSI1_OFFSET		12
224 #define MXC_CCM_CGR2_SSI1_MASK			(0x3 << 12)
225 #define MXC_CCM_CGR2_SSI2_OFFSET		14
226 #define MXC_CCM_CGR2_SSI2_MASK			(0x3 << 14)
227 #define MXC_CCM_CGR2_UART1_OFFSET		16
228 #define MXC_CCM_CGR2_UART1_MASK			(0x3 << 16)
229 #define MXC_CCM_CGR2_UART2_OFFSET		18
230 #define MXC_CCM_CGR2_UART2_MASK			(0x3 << 18)
231 #define MXC_CCM_CGR2_UART3_OFFSET		20
232 #define MXC_CCM_CGR2_UART3_MASK			(0x3 << 20)
233 #define MXC_CCM_CGR2_USBOTG_OFFSET		22
234 #define MXC_CCM_CGR2_USBOTG_MASK		(0x3 << 22)
235 #define MXC_CCM_CGR2_WDOG_OFFSET		24
236 #define MXC_CCM_CGR2_WDOG_MASK			(0x3 << 24)
237 #define MXC_CCM_CGR2_MAX_OFFSET			26
238 #define MXC_CCM_CGR2_MAX_MASK			(0x3 << 26)
239 #define MXC_CCM_CGR2_MAX_ENABLE			(0x2 << 26)
240 #define MXC_CCM_CGR2_AUDMUX_OFFSET		30
241 #define MXC_CCM_CGR2_AUDMUX_MASK		(0x3 << 30)
242 
243 #define MXC_CCM_CGR3_CSI_OFFSET			0
244 #define MXC_CCM_CGR3_CSI_MASK			(0x3 << 0)
245 #define MXC_CCM_CGR3_IIM_OFFSET			2
246 #define MXC_CCM_CGR3_IIM_MASK			(0x3 << 2)
247 #define MXC_CCM_CGR3_GPU2D_OFFSET		4
248 #define MXC_CCM_CGR3_GPU2D_MASK			(0x3 << 4)
249 
250 #define MXC_CCM_COSR_CLKOSEL_MASK		0x1F
251 #define MXC_CCM_COSR_CLKOSEL_OFFSET		0
252 #define MXC_CCM_COSR_CLKOEN			(1 << 5)
253 #define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
254 #define MXC_CCM_COSR_CLKOUT_PREDIV_MASK		(0x7 << 10)
255 #define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET	10
256 #define MXC_CCM_COSR_CLKOUT_PRODIV_MASK		(0x7 << 13)
257 #define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET	13
258 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
259 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
260 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
261 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET	18
262 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK	(0x3 << 20)
263 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET	20
264 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK	(0x3 << 22)
265 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET	22
266 #define MXC_CCM_COSR_ASRC_AUDIO_EN		(1 << 24)
267 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK	(0x3F << 26)
268 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET	26
269 
270 #endif
271