1 /* 2 * Copyright 2004-2009 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ 8 #define __CPU_ARM1136_MX35_CRM_REGS_H__ 9 10 /* Register bit definitions */ 11 #define MXC_CCM_CCMR_WFI (1 << 30) 12 #define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) 13 #define MXC_CCM_CCMR_VSTBY (1 << 28) 14 #define MXC_CCM_CCMR_WBEN (1 << 27) 15 #define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 16 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) 17 #define MXC_CCM_CCMR_ROMW_OFFSET 18 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) 19 #define MXC_CCM_CCMR_RAMW_OFFSET 16 20 #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) 21 #define MXC_CCM_CCMR_LPM_OFFSET 14 22 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 23 #define MXC_CCM_CCMR_UPE (1 << 9) 24 #define MXC_CCM_CCMR_MPE (1 << 3) 25 26 #define MXC_CCM_PDR0_PER_SEL (1 << 26) 27 #define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) 28 #define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 29 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) 30 #define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 31 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) 32 #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) 33 #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 34 #define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) 35 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 36 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) 37 #define MXC_CCM_PDR0_AUTO_CON 0x1 38 39 #define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 40 #define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) 41 #define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 42 #define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) 43 #define MXC_CCM_PDR1_MSHC_M_U (1 << 7) 44 45 #define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 46 #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) 47 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 48 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) 49 #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 50 #define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) 51 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 52 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) 53 #define MXC_CCM_PDR2_CSI_M_U (1 << 7) 54 #define MXC_CCM_PDR2_SSI_M_U (1 << 6) 55 #define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 56 #define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) 57 58 #define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 59 #define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) 60 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 61 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) 62 #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) 63 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 64 #define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) 65 #define MXC_CCM_PDR3_UART_M_U (1 << 14) 66 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 67 #define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) 68 #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) 69 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 70 #define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) 71 72 #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 73 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) 74 #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 75 #define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) 76 #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 77 #define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) 78 #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 79 #define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) 80 #define MXC_CCM_PDR4_USB_M_U (1 << 9) 81 82 /* Bit definitions for RCSR */ 83 #define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) 84 #define MXC_CCM_RCSR_BUS_16BIT (1 << 29) 85 #define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) 86 #define MXC_CCM_RCSR_PAGE_512 (0 << 27) 87 #define MXC_CCM_RCSR_PAGE_2K (1 << 27) 88 #define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) 89 #define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) 90 #define MXC_CCM_RCSR_SOFT_RESET (1 << 15) 91 #define MXC_CCM_RCSR_NF16B (1 << 14) 92 #define MXC_CCM_RCSR_NFC_4K (1 << 9) 93 #define MXC_CCM_RCSR_NFC_FMS (1 << 8) 94 95 /* Bit definitions for both MCU, PERIPHERAL PLL control registers */ 96 #define MXC_CCM_PCTL_BRM 0x80000000 97 #define MXC_CCM_PCTL_PD_OFFSET 26 98 #define MXC_CCM_PCTL_PD_MASK (0xF << 26) 99 #define MXC_CCM_PCTL_MFD_OFFSET 16 100 #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) 101 #define MXC_CCM_PCTL_MFI_OFFSET 10 102 #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) 103 #define MXC_CCM_PCTL_MFN_OFFSET 0 104 #define MXC_CCM_PCTL_MFN_MASK 0x3FF 105 106 /* Bit definitions for Audio clock mux register*/ 107 #define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 108 #define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) 109 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 110 #define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) 111 #define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 112 #define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) 113 #define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 114 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) 115 116 /* Bit definitions for Clock gating Register*/ 117 #define MXC_CCM_CGR_CG_MASK 0x3 118 #define MXC_CCM_CGR_CG_OFF 0x0 119 #define MXC_CCM_CGR_CG_RUN_ON 0x1 120 #define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 121 #define MXC_CCM_CGR_CG_ON 0x3 122 123 #define MXC_CCM_CGR0_ASRC_OFFSET 0 124 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) 125 #define MXC_CCM_CGR0_ATA_OFFSET 2 126 #define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) 127 #define MXC_CCM_CGR0_CAN1_OFFSET 6 128 #define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) 129 #define MXC_CCM_CGR0_CAN2_OFFSET 8 130 #define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) 131 #define MXC_CCM_CGR0_CSPI1_OFFSET 10 132 #define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) 133 #define MXC_CCM_CGR0_CSPI2_OFFSET 12 134 #define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) 135 #define MXC_CCM_CGR0_ECT_OFFSET 14 136 #define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) 137 #define MXC_CCM_CGR0_EDIO_OFFSET 16 138 #define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16) 139 #define MXC_CCM_CGR0_EMI_OFFSET 18 140 #define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) 141 #define MXC_CCM_CGR0_EPIT1_OFFSET 20 142 #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) 143 #define MXC_CCM_CGR0_EPIT2_OFFSET 22 144 #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) 145 #define MXC_CCM_CGR0_ESAI_OFFSET 24 146 #define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) 147 #define MXC_CCM_CGR0_ESDHC1_OFFSET 26 148 #define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) 149 #define MXC_CCM_CGR0_ESDHC2_OFFSET 28 150 #define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) 151 #define MXC_CCM_CGR0_ESDHC3_OFFSET 30 152 #define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) 153 154 #define MXC_CCM_CGR1_FEC_OFFSET 0 155 #define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) 156 #define MXC_CCM_CGR1_GPIO1_OFFSET 2 157 #define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) 158 #define MXC_CCM_CGR1_GPIO2_OFFSET 4 159 #define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) 160 #define MXC_CCM_CGR1_GPIO3_OFFSET 6 161 #define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) 162 #define MXC_CCM_CGR1_GPT_OFFSET 8 163 #define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) 164 #define MXC_CCM_CGR1_I2C1_OFFSET 10 165 #define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) 166 #define MXC_CCM_CGR1_I2C2_OFFSET 12 167 #define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) 168 #define MXC_CCM_CGR1_I2C3_OFFSET 14 169 #define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) 170 #define MXC_CCM_CGR1_IOMUXC_OFFSET 16 171 #define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) 172 #define MXC_CCM_CGR1_IPU_OFFSET 18 173 #define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) 174 #define MXC_CCM_CGR1_KPP_OFFSET 20 175 #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) 176 #define MXC_CCM_CGR1_MLB_OFFSET 22 177 #define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) 178 #define MXC_CCM_CGR1_MSHC_OFFSET 24 179 #define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) 180 #define MXC_CCM_CGR1_OWIRE_OFFSET 26 181 #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) 182 #define MXC_CCM_CGR1_PWM_OFFSET 28 183 #define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) 184 #define MXC_CCM_CGR1_RNGC_OFFSET 30 185 #define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) 186 187 #define MXC_CCM_CGR2_RTC_OFFSET 0 188 #define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) 189 #define MXC_CCM_CGR2_RTIC_OFFSET 2 190 #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) 191 #define MXC_CCM_CGR2_SCC_OFFSET 4 192 #define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) 193 #define MXC_CCM_CGR2_SDMA_OFFSET 6 194 #define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) 195 #define MXC_CCM_CGR2_SPBA_OFFSET 8 196 #define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) 197 #define MXC_CCM_CGR2_SPDIF_OFFSET 10 198 #define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) 199 #define MXC_CCM_CGR2_SSI1_OFFSET 12 200 #define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) 201 #define MXC_CCM_CGR2_SSI2_OFFSET 14 202 #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) 203 #define MXC_CCM_CGR2_UART1_OFFSET 16 204 #define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) 205 #define MXC_CCM_CGR2_UART2_OFFSET 18 206 #define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) 207 #define MXC_CCM_CGR2_UART3_OFFSET 20 208 #define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) 209 #define MXC_CCM_CGR2_USBOTG_OFFSET 22 210 #define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) 211 #define MXC_CCM_CGR2_WDOG_OFFSET 24 212 #define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) 213 #define MXC_CCM_CGR2_MAX_OFFSET 26 214 #define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) 215 #define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) 216 #define MXC_CCM_CGR2_AUDMUX_OFFSET 30 217 #define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) 218 219 #define MXC_CCM_CGR3_CSI_OFFSET 0 220 #define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) 221 #define MXC_CCM_CGR3_IIM_OFFSET 2 222 #define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) 223 #define MXC_CCM_CGR3_GPU2D_OFFSET 4 224 #define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) 225 226 #define MXC_CCM_COSR_CLKOSEL_MASK 0x1F 227 #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 228 #define MXC_CCM_COSR_CLKOEN (1 << 5) 229 #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) 230 #define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) 231 #define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 232 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) 233 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 234 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) 235 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 236 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) 237 #define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 238 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) 239 #define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 240 #define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) 241 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) 242 #define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 243 244 #endif 245