1 /* 2 * 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __ASM_ARCH_MX31_IMX_REGS_H 25 #define __ASM_ARCH_MX31_IMX_REGS_H 26 27 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 28 #include <asm/types.h> 29 30 /* Clock control module registers */ 31 struct clock_control_regs { 32 u32 ccmr; 33 u32 pdr0; 34 u32 pdr1; 35 u32 rcsr; 36 u32 mpctl; 37 u32 upctl; 38 u32 spctl; 39 u32 cosr; 40 u32 cgr0; 41 u32 cgr1; 42 u32 cgr2; 43 u32 wimr0; 44 u32 ldc; 45 u32 dcvr0; 46 u32 dcvr1; 47 u32 dcvr2; 48 u32 dcvr3; 49 u32 ltr0; 50 u32 ltr1; 51 u32 ltr2; 52 u32 ltr3; 53 u32 ltbr0; 54 u32 ltbr1; 55 u32 pmcr0; 56 u32 pmcr1; 57 u32 pdr2; 58 }; 59 60 /* GPIO Registers */ 61 struct gpio_regs { 62 u32 gpio_dr; 63 u32 gpio_dir; 64 u32 gpio_psr; 65 }; 66 67 struct cspi_regs { 68 u32 rxdata; 69 u32 txdata; 70 u32 ctrl; 71 u32 intr; 72 u32 dma; 73 u32 stat; 74 u32 period; 75 u32 test; 76 }; 77 78 /* Watchdog Timer (WDOG) registers */ 79 #define WDOG_ENABLE (1 << 2) 80 #define WDOG_WT_SHIFT 8 81 struct wdog_regs { 82 u16 wcr; /* Control */ 83 u16 wsr; /* Service */ 84 u16 wrsr; /* Reset Status */ 85 }; 86 87 /* IIM Control Registers */ 88 struct iim_regs { 89 u32 iim_stat; 90 u32 iim_statm; 91 u32 iim_err; 92 u32 iim_emask; 93 u32 iim_fctl; 94 u32 iim_ua; 95 u32 iim_la; 96 u32 iim_sdat; 97 u32 iim_prev; 98 u32 iim_srev; 99 u32 iim_prog_p; 100 u32 iim_scs0; 101 u32 iim_scs1; 102 u32 iim_scs2; 103 u32 iim_scs3; 104 }; 105 106 struct mx3_cpu_type { 107 u8 srev; 108 u32 v; 109 }; 110 111 #define IOMUX_PADNUM_MASK 0x1ff 112 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 113 114 /* 115 * various IOMUX pad functions 116 */ 117 enum iomux_pad_config { 118 PAD_CTL_NOLOOPBACK = 0x0 << 9, 119 PAD_CTL_LOOPBACK = 0x1 << 9, 120 PAD_CTL_PKE_NONE = 0x0 << 8, 121 PAD_CTL_PKE_ENABLE = 0x1 << 8, 122 PAD_CTL_PUE_KEEPER = 0x0 << 7, 123 PAD_CTL_PUE_PUD = 0x1 << 7, 124 PAD_CTL_100K_PD = 0x0 << 5, 125 PAD_CTL_100K_PU = 0x1 << 5, 126 PAD_CTL_47K_PU = 0x2 << 5, 127 PAD_CTL_22K_PU = 0x3 << 5, 128 PAD_CTL_HYS_CMOS = 0x0 << 4, 129 PAD_CTL_HYS_SCHMITZ = 0x1 << 4, 130 PAD_CTL_ODE_CMOS = 0x0 << 3, 131 PAD_CTL_ODE_OpenDrain = 0x1 << 3, 132 PAD_CTL_DRV_NORMAL = 0x0 << 1, 133 PAD_CTL_DRV_HIGH = 0x1 << 1, 134 PAD_CTL_DRV_MAX = 0x2 << 1, 135 PAD_CTL_SRE_SLOW = 0x0 << 0, 136 PAD_CTL_SRE_FAST = 0x1 << 0 137 }; 138 139 /* 140 * This enumeration is constructed based on the Section 141 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 142 * value is constructed based on the rules described above. 143 */ 144 145 enum iomux_pins { 146 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), 147 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), 148 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), 149 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), 150 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), 151 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), 152 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), 153 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), 154 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), 155 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), 156 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), 157 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), 158 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), 159 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), 160 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), 161 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), 162 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), 163 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), 164 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), 165 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), 166 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), 167 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), 168 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), 169 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), 170 MX31_PIN_READ = IOMUX_PIN(0xff, 24), 171 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), 172 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), 173 MX31_PIN_SER_RS = IOMUX_PIN(89, 27), 174 MX31_PIN_LCS1 = IOMUX_PIN(88, 28), 175 MX31_PIN_LCS0 = IOMUX_PIN(87, 29), 176 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), 177 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), 178 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), 179 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), 180 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), 181 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), 182 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), 183 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), 184 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), 185 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), 186 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), 187 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), 188 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), 189 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), 190 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), 191 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), 192 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), 193 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), 194 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), 195 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), 196 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), 197 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), 198 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), 199 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), 200 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), 201 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), 202 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), 203 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), 204 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), 205 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), 206 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), 207 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), 208 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), 209 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), 210 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), 211 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), 212 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), 213 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), 214 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), 215 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), 216 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), 217 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), 218 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), 219 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), 220 MX31_PIN_USB_OC = IOMUX_PIN(30, 74), 221 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), 222 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), 223 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), 224 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), 225 MX31_PIN_TDO = IOMUX_PIN(0xff, 79), 226 MX31_PIN_TDI = IOMUX_PIN(0xff, 80), 227 MX31_PIN_TMS = IOMUX_PIN(0xff, 81), 228 MX31_PIN_TCK = IOMUX_PIN(0xff, 82), 229 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), 230 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), 231 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), 232 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), 233 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), 234 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), 235 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), 236 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), 237 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), 238 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), 239 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), 240 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), 241 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), 242 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), 243 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), 244 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), 245 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), 246 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), 247 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), 248 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), 249 MX31_PIN_TXD2 = IOMUX_PIN(28, 103), 250 MX31_PIN_RXD2 = IOMUX_PIN(27, 104), 251 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), 252 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), 253 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), 254 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), 255 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), 256 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), 257 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), 258 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), 259 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), 260 MX31_PIN_CTS1 = IOMUX_PIN(39, 114), 261 MX31_PIN_RTS1 = IOMUX_PIN(38, 115), 262 MX31_PIN_TXD1 = IOMUX_PIN(37, 116), 263 MX31_PIN_RXD1 = IOMUX_PIN(36, 117), 264 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), 265 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), 266 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), 267 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), 268 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), 269 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), 270 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), 271 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), 272 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), 273 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), 274 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), 275 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), 276 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), 277 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), 278 MX31_PIN_SFS6 = IOMUX_PIN(26, 132), 279 MX31_PIN_SCK6 = IOMUX_PIN(25, 133), 280 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), 281 MX31_PIN_STXD6 = IOMUX_PIN(23, 135), 282 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), 283 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), 284 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), 285 MX31_PIN_STXD5 = IOMUX_PIN(21, 139), 286 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), 287 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), 288 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), 289 MX31_PIN_STXD4 = IOMUX_PIN(19, 143), 290 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), 291 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), 292 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), 293 MX31_PIN_STXD3 = IOMUX_PIN(17, 147), 294 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), 295 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), 296 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), 297 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), 298 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), 299 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), 300 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), 301 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), 302 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), 303 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), 304 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), 305 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), 306 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), 307 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), 308 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), 309 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), 310 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), 311 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), 312 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), 313 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), 314 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), 315 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), 316 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), 317 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), 318 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), 319 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), 320 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), 321 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), 322 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), 323 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), 324 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), 325 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), 326 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), 327 MX31_PIN_D0 = IOMUX_PIN(0xff, 181), 328 MX31_PIN_D1 = IOMUX_PIN(0xff, 182), 329 MX31_PIN_D2 = IOMUX_PIN(0xff, 183), 330 MX31_PIN_D3 = IOMUX_PIN(0xff, 184), 331 MX31_PIN_D4 = IOMUX_PIN(0xff, 185), 332 MX31_PIN_D5 = IOMUX_PIN(0xff, 186), 333 MX31_PIN_D6 = IOMUX_PIN(0xff, 187), 334 MX31_PIN_D7 = IOMUX_PIN(0xff, 188), 335 MX31_PIN_D8 = IOMUX_PIN(0xff, 189), 336 MX31_PIN_D9 = IOMUX_PIN(0xff, 190), 337 MX31_PIN_D10 = IOMUX_PIN(0xff, 191), 338 MX31_PIN_D11 = IOMUX_PIN(0xff, 192), 339 MX31_PIN_D12 = IOMUX_PIN(0xff, 193), 340 MX31_PIN_D13 = IOMUX_PIN(0xff, 194), 341 MX31_PIN_D14 = IOMUX_PIN(0xff, 195), 342 MX31_PIN_D15 = IOMUX_PIN(0xff, 196), 343 MX31_PIN_NFRB = IOMUX_PIN(16, 197), 344 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), 345 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), 346 MX31_PIN_NFCLE = IOMUX_PIN(13, 200), 347 MX31_PIN_NFALE = IOMUX_PIN(12, 201), 348 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), 349 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), 350 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), 351 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), 352 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), 353 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), 354 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), 355 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), 356 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), 357 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), 358 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), 359 MX31_PIN_CAS = IOMUX_PIN(0xff, 213), 360 MX31_PIN_RAS = IOMUX_PIN(0xff, 214), 361 MX31_PIN_RW = IOMUX_PIN(0xff, 215), 362 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), 363 MX31_PIN_LBA = IOMUX_PIN(0xff, 217), 364 MX31_PIN_ECB = IOMUX_PIN(0xff, 218), 365 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), 366 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), 367 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), 368 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), 369 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), 370 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), 371 MX31_PIN_OE = IOMUX_PIN(0xff, 225), 372 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), 373 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), 374 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), 375 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), 376 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), 377 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), 378 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), 379 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), 380 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), 381 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), 382 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), 383 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), 384 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), 385 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), 386 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), 387 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), 388 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), 389 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), 390 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), 391 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), 392 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), 393 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), 394 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), 395 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), 396 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), 397 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), 398 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), 399 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), 400 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), 401 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), 402 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), 403 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), 404 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), 405 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), 406 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), 407 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), 408 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), 409 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), 410 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), 411 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), 412 MX31_PIN_A25 = IOMUX_PIN(0xff, 266), 413 MX31_PIN_A24 = IOMUX_PIN(0xff, 267), 414 MX31_PIN_A23 = IOMUX_PIN(0xff, 268), 415 MX31_PIN_A22 = IOMUX_PIN(0xff, 269), 416 MX31_PIN_A21 = IOMUX_PIN(0xff, 270), 417 MX31_PIN_A20 = IOMUX_PIN(0xff, 271), 418 MX31_PIN_A19 = IOMUX_PIN(0xff, 272), 419 MX31_PIN_A18 = IOMUX_PIN(0xff, 273), 420 MX31_PIN_A17 = IOMUX_PIN(0xff, 274), 421 MX31_PIN_A16 = IOMUX_PIN(0xff, 275), 422 MX31_PIN_A14 = IOMUX_PIN(0xff, 276), 423 MX31_PIN_A15 = IOMUX_PIN(0xff, 277), 424 MX31_PIN_A13 = IOMUX_PIN(0xff, 278), 425 MX31_PIN_A12 = IOMUX_PIN(0xff, 279), 426 MX31_PIN_A11 = IOMUX_PIN(0xff, 280), 427 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), 428 MX31_PIN_A10 = IOMUX_PIN(0xff, 282), 429 MX31_PIN_A9 = IOMUX_PIN(0xff, 283), 430 MX31_PIN_A8 = IOMUX_PIN(0xff, 284), 431 MX31_PIN_A7 = IOMUX_PIN(0xff, 285), 432 MX31_PIN_A6 = IOMUX_PIN(0xff, 286), 433 MX31_PIN_A5 = IOMUX_PIN(0xff, 287), 434 MX31_PIN_A4 = IOMUX_PIN(0xff, 288), 435 MX31_PIN_A3 = IOMUX_PIN(0xff, 289), 436 MX31_PIN_A2 = IOMUX_PIN(0xff, 290), 437 MX31_PIN_A1 = IOMUX_PIN(0xff, 291), 438 MX31_PIN_A0 = IOMUX_PIN(0xff, 292), 439 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), 440 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), 441 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), 442 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), 443 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), 444 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), 445 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), 446 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), 447 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), 448 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), 449 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), 450 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), 451 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), 452 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), 453 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), 454 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), 455 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), 456 MX31_PIN_SRX0 = IOMUX_PIN(34, 310), 457 MX31_PIN_STX0 = IOMUX_PIN(33, 311), 458 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), 459 MX31_PIN_SRST0 = IOMUX_PIN(67, 313), 460 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), 461 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), 462 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), 463 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), 464 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), 465 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), 466 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), 467 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), 468 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), 469 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), 470 MX31_PIN_PWMO = IOMUX_PIN(9, 324), 471 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), 472 MX31_PIN_COMPARE = IOMUX_PIN(8, 326), 473 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), 474 }; 475 476 /* Bit definitions for RCSR register in CCM */ 477 #define CCM_RCSR_NF16B (1 << 31) 478 #define CCM_RCSR_NFMS (1 << 30) 479 480 #endif 481 482 #define __REG(x) (*((volatile u32 *)(x))) 483 #define __REG16(x) (*((volatile u16 *)(x))) 484 #define __REG8(x) (*((volatile u8 *)(x))) 485 486 #define CCM_BASE 0x53f80000 487 #define CCM_CCMR (CCM_BASE + 0x00) 488 #define CCM_PDR0 (CCM_BASE + 0x04) 489 #define CCM_PDR1 (CCM_BASE + 0x08) 490 #define CCM_RCSR (CCM_BASE + 0x0c) 491 #define CCM_MPCTL (CCM_BASE + 0x10) 492 #define CCM_UPCTL (CCM_BASE + 0x14) 493 #define CCM_SPCTL (CCM_BASE + 0x18) 494 #define CCM_COSR (CCM_BASE + 0x1C) 495 #define CCM_CGR0 (CCM_BASE + 0x20) 496 #define CCM_CGR1 (CCM_BASE + 0x24) 497 #define CCM_CGR2 (CCM_BASE + 0x28) 498 499 #define CCMR_MDS (1 << 7) 500 #define CCMR_SBYCS (1 << 4) 501 #define CCMR_MPE (1 << 3) 502 #define CCMR_PRCS_MASK (3 << 1) 503 #define CCMR_FPM (1 << 1) 504 #define CCMR_CKIH (2 << 1) 505 506 #define MX31_IIM_BASE_ADDR 0x5001C000 507 508 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) 509 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) 510 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) 511 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) 512 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) 513 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) 514 #define PDR0_MCU_PODF(x) ((x) & 0x7) 515 516 #define PLL_PD(x) (((x) & 0xf) << 26) 517 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 518 #define PLL_MFI(x) (((x) & 0xf) << 10) 519 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 520 521 #define WEIM_ESDCTL0 0xB8001000 522 #define WEIM_ESDCFG0 0xB8001004 523 #define WEIM_ESDCTL1 0xB8001008 524 #define WEIM_ESDCFG1 0xB800100C 525 #define WEIM_ESDMISC 0xB8001010 526 527 #define ESDCTL_SDE (1 << 31) 528 #define ESDCTL_CMD_RW (0 << 28) 529 #define ESDCTL_CMD_PRECHARGE (1 << 28) 530 #define ESDCTL_CMD_AUTOREFRESH (2 << 28) 531 #define ESDCTL_CMD_LOADMODEREG (3 << 28) 532 #define ESDCTL_CMD_MANUALREFRESH (4 << 28) 533 #define ESDCTL_ROW_13 (2 << 24) 534 #define ESDCTL_ROW(x) ((x) << 24) 535 #define ESDCTL_COL_9 (1 << 20) 536 #define ESDCTL_COL(x) ((x) << 20) 537 #define ESDCTL_DSIZ(x) ((x) << 16) 538 #define ESDCTL_SREFR(x) ((x) << 13) 539 #define ESDCTL_PWDT(x) ((x) << 10) 540 #define ESDCTL_FP(x) ((x) << 8) 541 #define ESDCTL_BL(x) ((x) << 7) 542 #define ESDCTL_PRCT(x) ((x) << 0) 543 544 #define WEIM_BASE 0xb8002000 545 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10) 546 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) 547 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) 548 549 #define IOMUXC_BASE 0x43FAC000 550 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) 551 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) 552 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) 553 554 #define IPU_BASE 0x53fc0000 555 #define IPU_CONF IPU_BASE 556 557 #define IPU_CONF_PXL_ENDIAN (1<<8) 558 #define IPU_CONF_DU_EN (1<<7) 559 #define IPU_CONF_DI_EN (1<<6) 560 #define IPU_CONF_ADC_EN (1<<5) 561 #define IPU_CONF_SDC_EN (1<<4) 562 #define IPU_CONF_PF_EN (1<<3) 563 #define IPU_CONF_ROT_EN (1<<2) 564 #define IPU_CONF_IC_EN (1<<1) 565 #define IPU_CONF_SCI_EN (1<<0) 566 567 #define ARM_PPMRR 0x40000015 568 569 #define WDOG_BASE 0x53FDC000 570 571 /* 572 * GPIO 573 */ 574 #define GPIO1_BASE_ADDR 0x53FCC000 575 #define GPIO2_BASE_ADDR 0x53FD0000 576 #define GPIO3_BASE_ADDR 0x53FA4000 577 #define GPIO_DR 0x00000000 /* data register */ 578 #define GPIO_GDIR 0x00000004 /* direction register */ 579 #define GPIO_PSR 0x00000008 /* pad status register */ 580 581 /* 582 * Signal Multiplexing (IOMUX) 583 */ 584 585 /* bits in the SW_MUX_CTL registers */ 586 #define MUX_CTL_OUT_GPIO_DR (0 << 4) 587 #define MUX_CTL_OUT_FUNC (1 << 4) 588 #define MUX_CTL_OUT_ALT1 (2 << 4) 589 #define MUX_CTL_OUT_ALT2 (3 << 4) 590 #define MUX_CTL_OUT_ALT3 (4 << 4) 591 #define MUX_CTL_OUT_ALT4 (5 << 4) 592 #define MUX_CTL_OUT_ALT5 (6 << 4) 593 #define MUX_CTL_OUT_ALT6 (7 << 4) 594 #define MUX_CTL_IN_NONE (0 << 0) 595 #define MUX_CTL_IN_GPIO (1 << 0) 596 #define MUX_CTL_IN_FUNC (2 << 0) 597 #define MUX_CTL_IN_ALT1 (4 << 0) 598 #define MUX_CTL_IN_ALT2 (8 << 0) 599 600 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) 601 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) 602 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) 603 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) 604 605 /* Register offsets based on IOMUXC_BASE */ 606 /* 0x00 .. 0x7b */ 607 #define MUX_CTL_USBH2_DATA1 0x40 608 #define MUX_CTL_USBH2_DIR 0x44 609 #define MUX_CTL_USBH2_STP 0x45 610 #define MUX_CTL_USBH2_NXT 0x46 611 #define MUX_CTL_USBH2_DATA0 0x47 612 #define MUX_CTL_USBH2_CLK 0x4B 613 #define MUX_CTL_RTS1 0x7c 614 #define MUX_CTL_CTS1 0x7d 615 #define MUX_CTL_DTR_DCE1 0x7e 616 #define MUX_CTL_DSR_DCE1 0x7f 617 #define MUX_CTL_CSPI2_SCLK 0x80 618 #define MUX_CTL_CSPI2_SPI_RDY 0x81 619 #define MUX_CTL_RXD1 0x82 620 #define MUX_CTL_TXD1 0x83 621 #define MUX_CTL_CSPI2_MISO 0x84 622 #define MUX_CTL_CSPI2_SS0 0x85 623 #define MUX_CTL_CSPI2_SS1 0x86 624 #define MUX_CTL_CSPI2_SS2 0x87 625 #define MUX_CTL_CSPI1_SS2 0x88 626 #define MUX_CTL_CSPI1_SCLK 0x89 627 #define MUX_CTL_CSPI1_SPI_RDY 0x8a 628 #define MUX_CTL_CSPI2_MOSI 0x8b 629 #define MUX_CTL_CSPI1_MOSI 0x8c 630 #define MUX_CTL_CSPI1_MISO 0x8d 631 #define MUX_CTL_CSPI1_SS0 0x8e 632 #define MUX_CTL_CSPI1_SS1 0x8f 633 #define MUX_CTL_STXD6 0x90 634 #define MUX_CTL_SRXD6 0x91 635 #define MUX_CTL_SCK6 0x92 636 #define MUX_CTL_SFS6 0x93 637 638 #define MUX_CTL_STXD3 0x9C 639 #define MUX_CTL_SRXD3 0x9D 640 #define MUX_CTL_SCK3 0x9E 641 #define MUX_CTL_SFS3 0x9F 642 643 #define MUX_CTL_NFC_WP 0xD0 644 #define MUX_CTL_NFC_CE 0xD1 645 #define MUX_CTL_NFC_RB 0xD2 646 #define MUX_CTL_NFC_WE 0xD4 647 #define MUX_CTL_NFC_RE 0xD5 648 #define MUX_CTL_NFC_ALE 0xD6 649 #define MUX_CTL_NFC_CLE 0xD7 650 651 652 #define MUX_CTL_CAPTURE 0x150 653 #define MUX_CTL_COMPARE 0x151 654 655 /* 656 * Helper macros for the MUX_[contact name]__[pin function] macros 657 */ 658 #define IOMUX_MODE_POS 9 659 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) 660 661 /* 662 * These macros can be used in mx31_gpio_mux() and have the form 663 * MUX_[contact name]__[pin function] 664 */ 665 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) 666 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) 667 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) 668 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) 669 670 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) 671 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) 672 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) 673 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) 674 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) 675 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ 676 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) 677 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) 678 679 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) 680 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) 681 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) 682 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) 683 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) 684 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ 685 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) 686 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) 687 688 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) 689 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) 690 691 /* PAD control registers for SDR/DDR */ 692 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) 693 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) 694 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) 695 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) 696 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) 697 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) 698 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) 699 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) 700 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) 701 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) 702 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) 703 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) 704 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) 705 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) 706 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) 707 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) 708 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) 709 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) 710 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) 711 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) 712 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) 713 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) 714 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) 715 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) 716 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) 717 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) 718 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) 719 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) 720 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) 721 722 /* 723 * Memory regions and CS 724 */ 725 #define IPU_MEM_BASE 0x70000000 726 #define CSD0_BASE 0x80000000 727 #define CSD1_BASE 0x90000000 728 #define CS0_BASE 0xA0000000 729 #define CS1_BASE 0xA8000000 730 #define CS2_BASE 0xB0000000 731 #define CS3_BASE 0xB2000000 732 #define CS4_BASE 0xB4000000 733 #define CS4_PSRAM_BASE 0xB5000000 734 #define CS5_BASE 0xB6000000 735 #define PCMCIA_MEM_BASE 0xC0000000 736 737 /* 738 * NAND controller 739 */ 740 #define NFC_BASE_ADDR 0xB8000000 741 742 /* 743 * Internal RAM (16KB) 744 */ 745 #define IRAM_BASE_ADDR 0x1FFFC000 746 #define IRAM_SIZE (16 * 1024) 747 748 #define MX31_AIPS1_BASE_ADDR 0x43f00000 749 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) 750 751 /* USB portsc */ 752 /* values for portsc field */ 753 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) 754 #define MXC_EHCI_FORCE_FS (1 << 24) 755 #define MXC_EHCI_UTMI_8BIT (0 << 28) 756 #define MXC_EHCI_UTMI_16BIT (1 << 28) 757 #define MXC_EHCI_SERIAL (1 << 29) 758 #define MXC_EHCI_MODE_UTMI (0 << 30) 759 #define MXC_EHCI_MODE_PHILIPS (1 << 30) 760 #define MXC_EHCI_MODE_ULPI (2 << 30) 761 #define MXC_EHCI_MODE_SERIAL (3 << 30) 762 763 /* values for flags field */ 764 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) 765 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) 766 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) 767 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) 768 #define MXC_EHCI_INTERFACE_MASK (0xf) 769 770 #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) 771 #define MXC_EHCI_TTL_ENABLED (1 << 6) 772 773 #define MXC_EHCI_INTERNAL_PHY (1 << 7) 774 #define MXC_EHCI_IPPUE_DOWN (1 << 8) 775 #define MXC_EHCI_IPPUE_UP (1 << 9) 776 777 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ 778