1 /*
2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3  * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #ifndef _IMX_REGS_H
25 #define _IMX_REGS_H
26 
27 #include <asm/arch/regs-rtc.h>
28 
29 #ifndef __ASSEMBLY__
30 
31 extern void imx_gpio_mode (int gpio_mode);
32 
33 #ifdef CONFIG_MXC_UART
34 extern void mx27_uart1_init_pins(void);
35 #endif /* CONFIG_MXC_UART */
36 
37 #ifdef CONFIG_FEC_MXC
38 extern void mx27_fec_init_pins(void);
39 #endif /* CONFIG_FEC_MXC */
40 
41 #ifdef CONFIG_MXC_MMC
42 extern void mx27_sd1_init_pins(void);
43 extern void mx27_sd2_init_pins(void);
44 #endif /* CONFIG_MXC_MMC */
45 
46 /* AIPI */
47 struct aipi_regs {
48 	u32 psr0;
49 	u32 psr1;
50 };
51 
52 /* System Control */
53 struct system_control_regs {
54 	u32 res[5];
55 	u32 fmcr;
56 	u32 gpcr;
57 	u32 wbcr;
58 	u32 dscr1;
59 	u32 dscr2;
60 	u32 dscr3;
61 	u32 dscr4;
62 	u32 dscr5;
63 	u32 dscr6;
64 	u32 dscr7;
65 	u32 dscr8;
66 	u32 dscr9;
67 	u32 dscr10;
68 	u32 dscr11;
69 	u32 dscr12;
70 	u32 dscr13;
71 	u32 pscr;
72 	u32 pmcr;
73 	u32 res1;
74 	u32 dcvr0;
75 	u32 dcvr1;
76 	u32 dcvr2;
77 	u32 dcvr3;
78 };
79 
80 /* Chip Select Registers */
81 struct weim_regs {
82 	u32 cs0u;	/* Chip Select 0 Upper Register */
83 	u32 cs0l;	/* Chip Select 0 Lower Register */
84 	u32 cs0a;	/* Chip Select 0 Addition Register */
85 	u32 pad0;
86 	u32 cs1u;	/* Chip Select 1 Upper Register */
87 	u32 cs1l;	/* Chip Select 1 Lower Register */
88 	u32 cs1a;	/* Chip Select 1 Addition Register */
89 	u32 pad1;
90 	u32 cs2u;	/* Chip Select 2 Upper Register */
91 	u32 cs2l;	/* Chip Select 2 Lower Register */
92 	u32 cs2a;	/* Chip Select 2 Addition Register */
93 	u32 pad2;
94 	u32 cs3u;	/* Chip Select 3 Upper Register */
95 	u32 cs3l;	/* Chip Select 3 Lower Register */
96 	u32 cs3a;	/* Chip Select 3 Addition Register */
97 	u32 pad3;
98 	u32 cs4u;	/* Chip Select 4 Upper Register */
99 	u32 cs4l;	/* Chip Select 4 Lower Register */
100 	u32 cs4a;	/* Chip Select 4 Addition Register */
101 	u32 pad4;
102 	u32 cs5u;	/* Chip Select 5 Upper Register */
103 	u32 cs5l;	/* Chip Select 5 Lower Register */
104 	u32 cs5a;	/* Chip Select 5 Addition Register */
105 	u32 pad5;
106 	u32 eim;	/* WEIM Configuration Register */
107 };
108 
109 /* SDRAM Controller registers */
110 struct esdramc_regs {
111 /* Enhanced SDRAM Control Register 0 */
112 	u32 esdctl0;
113 /* Enhanced SDRAM Configuration Register 0 */
114 	u32 esdcfg0;
115 /* Enhanced SDRAM Control Register 1 */
116 	u32 esdctl1;
117 /* Enhanced SDRAM Configuration Register 1 */
118 	u32 esdcfg1;
119 /* Enhanced SDRAM Miscellanious Register */
120 	u32 esdmisc;
121 };
122 
123 /* Watchdog Registers*/
124 struct wdog_regs {
125 	u32 wcr;
126 	u32 wsr;
127 	u32 wstr;
128 };
129 
130 /* PLL registers */
131 struct pll_regs {
132 	u32 cscr;	/* Clock Source Control Register */
133 	u32 mpctl0;	/* MCU PLL Control Register 0 */
134 	u32 mpctl1;	/* MCU PLL Control Register 1 */
135 	u32 spctl0;	/* System PLL Control Register 0 */
136 	u32 spctl1;	/* System PLL Control Register 1 */
137 	u32 osc26mctl;	/* Oscillator 26M Register */
138 	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
139 	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
140 	u32 pccr0;	/* Peripheral Clock Control Register 0 */
141 	u32 pccr1;	/* Peripheral Clock Control Register 1 */
142 	u32 ccsr;	/* Clock Control Status Register */
143 };
144 
145 /*
146  * Definitions for the clocksource registers
147  */
148 struct gpt_regs {
149 	u32 gpt_tctl;
150 	u32 gpt_tprer;
151 	u32 gpt_tcmp;
152 	u32 gpt_tcr;
153 	u32 gpt_tcn;
154 	u32 gpt_tstat;
155 };
156 
157 /*
158  *  GPIO Module and I/O Multiplexer
159  */
160 #define PORTA 0
161 #define PORTB 1
162 #define PORTC 2
163 #define PORTD 3
164 #define PORTE 4
165 #define PORTF 5
166 
167 /* IIM Control Registers */
168 struct iim_regs {
169 	u32 iim_stat;
170 	u32 iim_statm;
171 	u32 iim_err;
172 	u32 iim_emask;
173 	u32 iim_fctl;
174 	u32 iim_ua;
175 	u32 iim_la;
176 	u32 iim_sdat;
177 	u32 iim_prev;
178 	u32 iim_srev;
179 	u32 iim_prg_p;
180 	u32 iim_scs0;
181 	u32 iim_scs1;
182 	u32 iim_scs2;
183 	u32 iim_scs3;
184 	u32 res[0x1f1];
185 	struct fuse_bank {
186 		u32 fuse_regs[0x20];
187 		u32 fuse_rsvd[0xe0];
188 	} bank[1];
189 };
190 
191 struct fuse_bank0_regs {
192 	u32 fuse0_3[5];
193 	u32 mac_addr[6];
194 	u32 fuse10_31[0x16];
195 };
196 
197 #endif
198 
199 #define ARCH_MXC
200 
201 #define IMX_IO_BASE		0x10000000
202 
203 #define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
204 #define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
205 #define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
206 #define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
207 #define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
208 #define IMX_RTC_BASE		(0x07000 + IMX_IO_BASE)
209 #define UART1_BASE		(0x0a000 + IMX_IO_BASE)
210 #define UART2_BASE		(0x0b000 + IMX_IO_BASE)
211 #define UART3_BASE		(0x0c000 + IMX_IO_BASE)
212 #define UART4_BASE		(0x0d000 + IMX_IO_BASE)
213 #define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
214 #define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
215 #define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
216 #define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
217 #define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
218 #define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
219 #define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
220 #define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
221 #define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
222 #define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
223 #define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
224 #define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
225 #define IIM_BASE_ADDR		IMX_IIM_BASE
226 #define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
227 
228 #define IMX_ESD_BASE		(0xD8001000)
229 #define IMX_WEIM_BASE		(0xD8002000)
230 
231 /* FMCR System Control bit definition*/
232 #define UART4_RXD_CTL	(1 << 25)
233 #define UART4_RTS_CTL	(1 << 24)
234 #define KP_COL6_CTL	(1 << 18)
235 #define KP_ROW7_CTL	(1 << 17)
236 #define KP_ROW6_CTL	(1 << 16)
237 #define PC_WAIT_B_CTL	(1 << 14)
238 #define PC_READY_CTL	(1 << 13)
239 #define PC_VS1_CTL	(1 << 12)
240 #define PC_VS2_CTL	(1 << 11)
241 #define PC_BVD1_CTL	(1 << 10)
242 #define PC_BVD2_CTL	(1 << 9)
243 #define IOS16_CTL	(1 << 8)
244 #define NF_FMS		(1 << 5)
245 #define NF_16BIT_SEL	(1 << 4)
246 #define SLCDC_SEL	(1 << 2)
247 #define SDCS1_SEL	(1 << 1)
248 #define SDCS0_SEL	(1 << 0)
249 
250 
251 /* important definition of some bits of WCR */
252 #define WCR_WDE 0x04
253 
254 #define CSCR_MPEN		(1 << 0)
255 #define CSCR_SPEN		(1 << 1)
256 #define CSCR_FPM_EN		(1 << 2)
257 #define CSCR_OSC26M_DIS		(1 << 3)
258 #define CSCR_OSC26M_DIV1P5	(1 << 4)
259 #define CSCR_AHB_DIV
260 #define CSCR_ARM_DIV
261 #define CSCR_ARM_SRC_MPLL	(1 << 15)
262 #define CSCR_MCU_SEL		(1 << 16)
263 #define CSCR_SP_SEL		(1 << 17)
264 #define CSCR_MPLL_RESTART	(1 << 18)
265 #define CSCR_SPLL_RESTART	(1 << 19)
266 #define CSCR_MSHC_SEL		(1 << 20)
267 #define CSCR_H264_SEL		(1 << 21)
268 #define CSCR_SSI1_SEL		(1 << 22)
269 #define CSCR_SSI2_SEL		(1 << 23)
270 #define CSCR_SD_CNT
271 #define CSCR_USB_DIV
272 #define CSCR_UPDATE_DIS		(1 << 31)
273 
274 #define MPCTL1_BRMO		(1 << 6)
275 #define MPCTL1_LF		(1 << 15)
276 
277 #define PCCR0_SSI2_EN	(1 << 0)
278 #define PCCR0_SSI1_EN	(1 << 1)
279 #define PCCR0_SLCDC_EN	(1 << 2)
280 #define PCCR0_SDHC3_EN	(1 << 3)
281 #define PCCR0_SDHC2_EN	(1 << 4)
282 #define PCCR0_SDHC1_EN	(1 << 5)
283 #define PCCR0_SDC_EN	(1 << 6)
284 #define PCCR0_SAHARA_EN	(1 << 7)
285 #define PCCR0_RTIC_EN	(1 << 8)
286 #define PCCR0_RTC_EN	(1 << 9)
287 #define PCCR0_PWM_EN	(1 << 11)
288 #define PCCR0_OWIRE_EN	(1 << 12)
289 #define PCCR0_MSHC_EN	(1 << 13)
290 #define PCCR0_LCDC_EN	(1 << 14)
291 #define PCCR0_KPP_EN	(1 << 15)
292 #define PCCR0_IIM_EN	(1 << 16)
293 #define PCCR0_I2C2_EN	(1 << 17)
294 #define PCCR0_I2C1_EN	(1 << 18)
295 #define PCCR0_GPT6_EN	(1 << 19)
296 #define PCCR0_GPT5_EN	(1 << 20)
297 #define PCCR0_GPT4_EN	(1 << 21)
298 #define PCCR0_GPT3_EN	(1 << 22)
299 #define PCCR0_GPT2_EN	(1 << 23)
300 #define PCCR0_GPT1_EN	(1 << 24)
301 #define PCCR0_GPIO_EN	(1 << 25)
302 #define PCCR0_FEC_EN	(1 << 26)
303 #define PCCR0_EMMA_EN	(1 << 27)
304 #define PCCR0_DMA_EN	(1 << 28)
305 #define PCCR0_CSPI3_EN	(1 << 29)
306 #define PCCR0_CSPI2_EN	(1 << 30)
307 #define PCCR0_CSPI1_EN	(1 << 31)
308 
309 #define PCCR1_MSHC_BAUDEN	(1 << 2)
310 #define PCCR1_NFC_BAUDEN	(1 << 3)
311 #define PCCR1_SSI2_BAUDEN	(1 << 4)
312 #define PCCR1_SSI1_BAUDEN	(1 << 5)
313 #define PCCR1_H264_BAUDEN	(1 << 6)
314 #define PCCR1_PERCLK4_EN	(1 << 7)
315 #define PCCR1_PERCLK3_EN	(1 << 8)
316 #define PCCR1_PERCLK2_EN	(1 << 9)
317 #define PCCR1_PERCLK1_EN	(1 << 10)
318 #define PCCR1_HCLK_USB		(1 << 11)
319 #define PCCR1_HCLK_SLCDC	(1 << 12)
320 #define PCCR1_HCLK_SAHARA	(1 << 13)
321 #define PCCR1_HCLK_RTIC		(1 << 14)
322 #define PCCR1_HCLK_LCDC		(1 << 15)
323 #define PCCR1_HCLK_H264		(1 << 16)
324 #define PCCR1_HCLK_FEC		(1 << 17)
325 #define PCCR1_HCLK_EMMA		(1 << 18)
326 #define PCCR1_HCLK_EMI		(1 << 19)
327 #define PCCR1_HCLK_DMA		(1 << 20)
328 #define PCCR1_HCLK_CSI		(1 << 21)
329 #define PCCR1_HCLK_BROM		(1 << 22)
330 #define PCCR1_HCLK_ATA		(1 << 23)
331 #define PCCR1_WDT_EN		(1 << 24)
332 #define PCCR1_USB_EN		(1 << 25)
333 #define PCCR1_UART6_EN		(1 << 26)
334 #define PCCR1_UART5_EN		(1 << 27)
335 #define PCCR1_UART4_EN		(1 << 28)
336 #define PCCR1_UART3_EN		(1 << 29)
337 #define PCCR1_UART2_EN		(1 << 30)
338 #define PCCR1_UART1_EN		(1 << 31)
339 
340 /* SDRAM Controller registers bitfields */
341 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
342 #define ESDCTL_BL		(1 << 7)
343 #define ESDCTL_FP		(1 << 8)
344 #define ESDCTL_PWDT(x)		(((x) & 3) << 10)
345 #define ESDCTL_SREFR(x)		(((x) & 7) << 13)
346 #define ESDCTL_DSIZ_16_UPPER	(0 << 16)
347 #define ESDCTL_DSIZ_16_LOWER	(1 << 16)
348 #define ESDCTL_DSIZ_32		(2 << 16)
349 #define ESDCTL_COL8		(0 << 20)
350 #define ESDCTL_COL9		(1 << 20)
351 #define ESDCTL_COL10		(2 << 20)
352 #define ESDCTL_ROW11		(0 << 24)
353 #define ESDCTL_ROW12		(1 << 24)
354 #define ESDCTL_ROW13		(2 << 24)
355 #define ESDCTL_ROW14		(3 << 24)
356 #define ESDCTL_ROW15		(4 << 24)
357 #define ESDCTL_SP		(1 << 27)
358 #define ESDCTL_SMODE_NORMAL	(0 << 28)
359 #define ESDCTL_SMODE_PRECHARGE	(1 << 28)
360 #define ESDCTL_SMODE_AUTO_REF	(2 << 28)
361 #define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
362 #define ESDCTL_SMODE_MAN_REF	(4 << 28)
363 #define ESDCTL_SDE		(1 << 31)
364 
365 #define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
366 #define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
367 #define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
368 #define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
369 #define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
370 #define ESDCFG_TWR		(1 << 15)
371 #define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
372 #define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
373 #define ESDCFG_TWTR		(1 << 20)
374 #define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
375 
376 #define ESDMISC_RST		(1 << 1)
377 #define ESDMISC_MDDREN		(1 << 2)
378 #define ESDMISC_MDDR_DL_RST	(1 << 3)
379 #define ESDMISC_MDDR_MDIS	(1 << 4)
380 #define ESDMISC_LHD		(1 << 5)
381 #define ESDMISC_MA10_SHARE	(1 << 6)
382 #define ESDMISC_SDRAM_RDY	(1 << 31)
383 
384 #define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
385 #define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
386 #define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
387 #define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
388 #define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
389 #define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
390 #define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
391 #define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
392 #define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
393 
394 #define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
395 #define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
396 #define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
397 #define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
398 #define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
399 #define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
400 #define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
401 #define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
402 #define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
403 #define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
404 #define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
405 #define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
406 #define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
407 #define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
408 #define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
409 #define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
410 #define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
411 #define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
412 
413 #define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
414 #define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
415 #define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
416 #define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
417 #define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
418 #define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
419 #define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
420 #define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
421 #define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
422 #define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
423 #define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
424 #define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
425 #define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
426 #define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
427 #define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
428 #define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
429 #define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
430 #define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
431 #define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
432 #define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
433 #define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
434 #define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
435 #define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
436 #define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
437 #define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
438 #define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
439 #define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
440 #define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
441 #define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
442 #define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
443 #define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
444 
445 /* Clocksource Bitfields */
446 #define TCTL_SWR	(1 << 15)	/* Software reset */
447 #define TCTL_FRR	(1 << 8)	/* Freerun / restart */
448 #define TCTL_CAP	(3 << 6)	/* Capture Edge */
449 #define TCTL_OM		(1 << 5)	/* output mode */
450 #define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
451 #define TCTL_CLKSOURCE	1		/* Clock source bit position */
452 #define TCTL_TEN	1		/* Timer enable */
453 #define TPRER_PRES	0xff		/* Prescale */
454 #define TSTAT_CAPT	(1 << 1)	/* Capture event */
455 #define TSTAT_COMP	1		/* Compare event */
456 
457 #define GPIO1_BASE_ADDR 0x10015000
458 #define GPIO2_BASE_ADDR 0x10015100
459 #define GPIO3_BASE_ADDR 0x10015200
460 #define GPIO4_BASE_ADDR 0x10015300
461 #define GPIO5_BASE_ADDR 0x10015400
462 #define GPIO6_BASE_ADDR 0x10015500
463 
464 #define GPIO_PIN_MASK	0x1f
465 
466 #define GPIO_PORT_SHIFT	5
467 #define GPIO_PORT_MASK	(0x7 << GPIO_PORT_SHIFT)
468 
469 #define GPIO_PORTA	(PORTA << GPIO_PORT_SHIFT)
470 #define GPIO_PORTB	(PORTB << GPIO_PORT_SHIFT)
471 #define GPIO_PORTC	(PORTC << GPIO_PORT_SHIFT)
472 #define GPIO_PORTD	(PORTD << GPIO_PORT_SHIFT)
473 #define GPIO_PORTE	(PORTE << GPIO_PORT_SHIFT)
474 #define GPIO_PORTF	(PORTF << GPIO_PORT_SHIFT)
475 
476 #define GPIO_OUT	(1 << 8)
477 #define GPIO_IN		(0 << 8)
478 #define GPIO_PUEN	(1 << 9)
479 
480 #define GPIO_PF		(1 << 10)
481 #define GPIO_AF		(1 << 11)
482 
483 #define GPIO_OCR_SHIFT	12
484 #define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
485 #define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
486 #define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
487 #define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
488 #define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)
489 
490 #define GPIO_AOUT_SHIFT	14
491 #define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
492 #define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
493 #define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
494 #define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
495 #define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)
496 
497 #define GPIO_BOUT_SHIFT	16
498 #define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
499 #define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
500 #define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
501 #define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
502 #define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
503 
504 #define IIM_STAT_BUSY	(1 << 7)
505 #define IIM_STAT_PRGD	(1 << 1)
506 #define IIM_STAT_SNSD	(1 << 0)
507 #define IIM_ERR_PRGE	(1 << 7)
508 #define IIM_ERR_WPE	(1 << 6)
509 #define IIM_ERR_OPE	(1 << 5)
510 #define IIM_ERR_RPE	(1 << 4)
511 #define IIM_ERR_WLRE	(1 << 3)
512 #define IIM_ERR_SNSE	(1 << 2)
513 #define IIM_ERR_PARITYE	(1 << 1)
514 
515 #endif				/* _IMX_REGS_H */
516