1 /* 2 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 3 * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _IMX_REGS_H 25 #define _IMX_REGS_H 26 27 #ifndef __ASSEMBLY__ 28 29 extern void imx_gpio_mode (int gpio_mode); 30 31 #ifdef CONFIG_MXC_UART 32 extern void mx27_uart1_init_pins(void); 33 #endif /* CONFIG_MXC_UART */ 34 35 #ifdef CONFIG_FEC_MXC 36 extern void mx27_fec_init_pins(void); 37 extern void imx_get_mac_from_fuse(unsigned char *mac); 38 #endif /* CONFIG_FEC_MXC */ 39 40 #ifdef CONFIG_MXC_MMC 41 extern void mx27_sd1_init_pins(void); 42 extern void mx27_sd2_init_pins(void); 43 #endif /* CONFIG_MXC_MMC */ 44 45 /* AIPI */ 46 struct aipi_regs { 47 u32 psr0; 48 u32 psr1; 49 }; 50 51 /* System Control */ 52 struct system_control_regs { 53 u32 res[5]; 54 u32 fmcr; 55 u32 gpcr; 56 u32 wbcr; 57 u32 dscr1; 58 u32 dscr2; 59 u32 dscr3; 60 u32 dscr4; 61 u32 dscr5; 62 u32 dscr6; 63 u32 dscr7; 64 u32 dscr8; 65 u32 dscr9; 66 u32 dscr10; 67 u32 dscr11; 68 u32 dscr12; 69 u32 dscr13; 70 u32 pscr; 71 u32 pmcr; 72 u32 res1; 73 u32 dcvr0; 74 u32 dcvr1; 75 u32 dcvr2; 76 u32 dcvr3; 77 }; 78 79 /* Chip Select Registers */ 80 struct weim_regs { 81 u32 cs0u; /* Chip Select 0 Upper Register */ 82 u32 cs0l; /* Chip Select 0 Lower Register */ 83 u32 cs0a; /* Chip Select 0 Addition Register */ 84 u32 pad0; 85 u32 cs1u; /* Chip Select 1 Upper Register */ 86 u32 cs1l; /* Chip Select 1 Lower Register */ 87 u32 cs1a; /* Chip Select 1 Addition Register */ 88 u32 pad1; 89 u32 cs2u; /* Chip Select 2 Upper Register */ 90 u32 cs2l; /* Chip Select 2 Lower Register */ 91 u32 cs2a; /* Chip Select 2 Addition Register */ 92 u32 pad2; 93 u32 cs3u; /* Chip Select 3 Upper Register */ 94 u32 cs3l; /* Chip Select 3 Lower Register */ 95 u32 cs3a; /* Chip Select 3 Addition Register */ 96 u32 pad3; 97 u32 cs4u; /* Chip Select 4 Upper Register */ 98 u32 cs4l; /* Chip Select 4 Lower Register */ 99 u32 cs4a; /* Chip Select 4 Addition Register */ 100 u32 pad4; 101 u32 cs5u; /* Chip Select 5 Upper Register */ 102 u32 cs5l; /* Chip Select 5 Lower Register */ 103 u32 cs5a; /* Chip Select 5 Addition Register */ 104 u32 pad5; 105 u32 eim; /* WEIM Configuration Register */ 106 }; 107 108 /* SDRAM Controller registers */ 109 struct esdramc_regs { 110 /* Enhanced SDRAM Control Register 0 */ 111 u32 esdctl0; 112 /* Enhanced SDRAM Configuration Register 0 */ 113 u32 esdcfg0; 114 /* Enhanced SDRAM Control Register 1 */ 115 u32 esdctl1; 116 /* Enhanced SDRAM Configuration Register 1 */ 117 u32 esdcfg1; 118 /* Enhanced SDRAM Miscellanious Register */ 119 u32 esdmisc; 120 }; 121 122 /* Watchdog Registers*/ 123 struct wdog_regs { 124 u32 wcr; 125 u32 wsr; 126 u32 wstr; 127 }; 128 129 /* PLL registers */ 130 struct pll_regs { 131 u32 cscr; /* Clock Source Control Register */ 132 u32 mpctl0; /* MCU PLL Control Register 0 */ 133 u32 mpctl1; /* MCU PLL Control Register 1 */ 134 u32 spctl0; /* System PLL Control Register 0 */ 135 u32 spctl1; /* System PLL Control Register 1 */ 136 u32 osc26mctl; /* Oscillator 26M Register */ 137 u32 pcdr0; /* Peripheral Clock Divider Register 0 */ 138 u32 pcdr1; /* Peripheral Clock Divider Register 1 */ 139 u32 pccr0; /* Peripheral Clock Control Register 0 */ 140 u32 pccr1; /* Peripheral Clock Control Register 1 */ 141 u32 ccsr; /* Clock Control Status Register */ 142 }; 143 144 /* 145 * Definitions for the clocksource registers 146 */ 147 struct gpt_regs { 148 u32 gpt_tctl; 149 u32 gpt_tprer; 150 u32 gpt_tcmp; 151 u32 gpt_tcr; 152 u32 gpt_tcn; 153 u32 gpt_tstat; 154 }; 155 156 /* 157 * GPIO Module and I/O Multiplexer 158 */ 159 #define PORTA 0 160 #define PORTB 1 161 #define PORTC 2 162 #define PORTD 3 163 #define PORTE 4 164 #define PORTF 5 165 166 struct gpio_regs { 167 struct { 168 u32 ddir; 169 u32 ocr1; 170 u32 ocr2; 171 u32 iconfa1; 172 u32 iconfa2; 173 u32 iconfb1; 174 u32 iconfb2; 175 u32 dr; 176 u32 gius; 177 u32 ssr; 178 u32 icr1; 179 u32 icr2; 180 u32 imr; 181 u32 isr; 182 u32 gpr; 183 u32 swr; 184 u32 puen; 185 u32 res[0x2f]; 186 } port[6]; 187 }; 188 189 /* IIM Control Registers */ 190 struct iim_regs { 191 u32 iim_stat; 192 u32 iim_statm; 193 u32 iim_err; 194 u32 iim_emask; 195 u32 iim_fctl; 196 u32 iim_ua; 197 u32 iim_la; 198 u32 iim_sdat; 199 u32 iim_prev; 200 u32 iim_srev; 201 u32 iim_prog_p; 202 u32 iim_scs0; 203 u32 iim_scs1; 204 u32 iim_scs2; 205 u32 iim_scs3; 206 u32 res[0x1f1]; 207 struct fuse_bank { 208 u32 fuse_regs[0x20]; 209 u32 fuse_rsvd[0xe0]; 210 } bank[1]; 211 }; 212 213 struct fuse_bank0_regs { 214 u32 fuse0_3[5]; 215 u32 mac_addr[6]; 216 u32 fuse10_31[0x16]; 217 }; 218 219 #endif 220 221 #define IMX_IO_BASE 0x10000000 222 223 #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) 224 #define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) 225 #define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) 226 #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) 227 #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) 228 #define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) 229 #define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) 230 #define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) 231 #define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) 232 #define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) 233 #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) 234 #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) 235 #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) 236 #define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) 237 #define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) 238 #define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) 239 #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) 240 #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) 241 #define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) 242 #define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) 243 #define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) 244 #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) 245 246 #define IMX_ESD_BASE (0xD8001000) 247 #define IMX_WEIM_BASE (0xD8002000) 248 249 /* FMCR System Control bit definition*/ 250 #define UART4_RXD_CTL (1 << 25) 251 #define UART4_RTS_CTL (1 << 24) 252 #define KP_COL6_CTL (1 << 18) 253 #define KP_ROW7_CTL (1 << 17) 254 #define KP_ROW6_CTL (1 << 16) 255 #define PC_WAIT_B_CTL (1 << 14) 256 #define PC_READY_CTL (1 << 13) 257 #define PC_VS1_CTL (1 << 12) 258 #define PC_VS2_CTL (1 << 11) 259 #define PC_BVD1_CTL (1 << 10) 260 #define PC_BVD2_CTL (1 << 9) 261 #define IOS16_CTL (1 << 8) 262 #define NF_FMS (1 << 5) 263 #define NF_16BIT_SEL (1 << 4) 264 #define SLCDC_SEL (1 << 2) 265 #define SDCS1_SEL (1 << 1) 266 #define SDCS0_SEL (1 << 0) 267 268 269 /* important definition of some bits of WCR */ 270 #define WCR_WDE 0x04 271 272 #define CSCR_MPEN (1 << 0) 273 #define CSCR_SPEN (1 << 1) 274 #define CSCR_FPM_EN (1 << 2) 275 #define CSCR_OSC26M_DIS (1 << 3) 276 #define CSCR_OSC26M_DIV1P5 (1 << 4) 277 #define CSCR_AHB_DIV 278 #define CSCR_ARM_DIV 279 #define CSCR_ARM_SRC_MPLL (1 << 15) 280 #define CSCR_MCU_SEL (1 << 16) 281 #define CSCR_SP_SEL (1 << 17) 282 #define CSCR_MPLL_RESTART (1 << 18) 283 #define CSCR_SPLL_RESTART (1 << 19) 284 #define CSCR_MSHC_SEL (1 << 20) 285 #define CSCR_H264_SEL (1 << 21) 286 #define CSCR_SSI1_SEL (1 << 22) 287 #define CSCR_SSI2_SEL (1 << 23) 288 #define CSCR_SD_CNT 289 #define CSCR_USB_DIV 290 #define CSCR_UPDATE_DIS (1 << 31) 291 292 #define MPCTL1_BRMO (1 << 6) 293 #define MPCTL1_LF (1 << 15) 294 295 #define PCCR0_SSI2_EN (1 << 0) 296 #define PCCR0_SSI1_EN (1 << 1) 297 #define PCCR0_SLCDC_EN (1 << 2) 298 #define PCCR0_SDHC3_EN (1 << 3) 299 #define PCCR0_SDHC2_EN (1 << 4) 300 #define PCCR0_SDHC1_EN (1 << 5) 301 #define PCCR0_SDC_EN (1 << 6) 302 #define PCCR0_SAHARA_EN (1 << 7) 303 #define PCCR0_RTIC_EN (1 << 8) 304 #define PCCR0_RTC_EN (1 << 9) 305 #define PCCR0_PWM_EN (1 << 11) 306 #define PCCR0_OWIRE_EN (1 << 12) 307 #define PCCR0_MSHC_EN (1 << 13) 308 #define PCCR0_LCDC_EN (1 << 14) 309 #define PCCR0_KPP_EN (1 << 15) 310 #define PCCR0_IIM_EN (1 << 16) 311 #define PCCR0_I2C2_EN (1 << 17) 312 #define PCCR0_I2C1_EN (1 << 18) 313 #define PCCR0_GPT6_EN (1 << 19) 314 #define PCCR0_GPT5_EN (1 << 20) 315 #define PCCR0_GPT4_EN (1 << 21) 316 #define PCCR0_GPT3_EN (1 << 22) 317 #define PCCR0_GPT2_EN (1 << 23) 318 #define PCCR0_GPT1_EN (1 << 24) 319 #define PCCR0_GPIO_EN (1 << 25) 320 #define PCCR0_FEC_EN (1 << 26) 321 #define PCCR0_EMMA_EN (1 << 27) 322 #define PCCR0_DMA_EN (1 << 28) 323 #define PCCR0_CSPI3_EN (1 << 29) 324 #define PCCR0_CSPI2_EN (1 << 30) 325 #define PCCR0_CSPI1_EN (1 << 31) 326 327 #define PCCR1_MSHC_BAUDEN (1 << 2) 328 #define PCCR1_NFC_BAUDEN (1 << 3) 329 #define PCCR1_SSI2_BAUDEN (1 << 4) 330 #define PCCR1_SSI1_BAUDEN (1 << 5) 331 #define PCCR1_H264_BAUDEN (1 << 6) 332 #define PCCR1_PERCLK4_EN (1 << 7) 333 #define PCCR1_PERCLK3_EN (1 << 8) 334 #define PCCR1_PERCLK2_EN (1 << 9) 335 #define PCCR1_PERCLK1_EN (1 << 10) 336 #define PCCR1_HCLK_USB (1 << 11) 337 #define PCCR1_HCLK_SLCDC (1 << 12) 338 #define PCCR1_HCLK_SAHARA (1 << 13) 339 #define PCCR1_HCLK_RTIC (1 << 14) 340 #define PCCR1_HCLK_LCDC (1 << 15) 341 #define PCCR1_HCLK_H264 (1 << 16) 342 #define PCCR1_HCLK_FEC (1 << 17) 343 #define PCCR1_HCLK_EMMA (1 << 18) 344 #define PCCR1_HCLK_EMI (1 << 19) 345 #define PCCR1_HCLK_DMA (1 << 20) 346 #define PCCR1_HCLK_CSI (1 << 21) 347 #define PCCR1_HCLK_BROM (1 << 22) 348 #define PCCR1_HCLK_ATA (1 << 23) 349 #define PCCR1_WDT_EN (1 << 24) 350 #define PCCR1_USB_EN (1 << 25) 351 #define PCCR1_UART6_EN (1 << 26) 352 #define PCCR1_UART5_EN (1 << 27) 353 #define PCCR1_UART4_EN (1 << 28) 354 #define PCCR1_UART3_EN (1 << 29) 355 #define PCCR1_UART2_EN (1 << 30) 356 #define PCCR1_UART1_EN (1 << 31) 357 358 /* SDRAM Controller registers bitfields */ 359 #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) 360 #define ESDCTL_BL (1 << 7) 361 #define ESDCTL_FP (1 << 8) 362 #define ESDCTL_PWDT(x) (((x) & 3) << 10) 363 #define ESDCTL_SREFR(x) (((x) & 7) << 13) 364 #define ESDCTL_DSIZ_16_UPPER (0 << 16) 365 #define ESDCTL_DSIZ_16_LOWER (1 << 16) 366 #define ESDCTL_DSIZ_32 (2 << 16) 367 #define ESDCTL_COL8 (0 << 20) 368 #define ESDCTL_COL9 (1 << 20) 369 #define ESDCTL_COL10 (2 << 20) 370 #define ESDCTL_ROW11 (0 << 24) 371 #define ESDCTL_ROW12 (1 << 24) 372 #define ESDCTL_ROW13 (2 << 24) 373 #define ESDCTL_ROW14 (3 << 24) 374 #define ESDCTL_ROW15 (4 << 24) 375 #define ESDCTL_SP (1 << 27) 376 #define ESDCTL_SMODE_NORMAL (0 << 28) 377 #define ESDCTL_SMODE_PRECHARGE (1 << 28) 378 #define ESDCTL_SMODE_AUTO_REF (2 << 28) 379 #define ESDCTL_SMODE_LOAD_MODE (3 << 28) 380 #define ESDCTL_SMODE_MAN_REF (4 << 28) 381 #define ESDCTL_SDE (1 << 31) 382 383 #define ESDCFG_TRC(x) (((x) & 0xf) << 0) 384 #define ESDCFG_TRCD(x) (((x) & 0x7) << 4) 385 #define ESDCFG_TCAS(x) (((x) & 0x3) << 8) 386 #define ESDCFG_TRRD(x) (((x) & 0x3) << 10) 387 #define ESDCFG_TRAS(x) (((x) & 0x7) << 12) 388 #define ESDCFG_TWR (1 << 15) 389 #define ESDCFG_TMRD(x) (((x) & 0x3) << 16) 390 #define ESDCFG_TRP(x) (((x) & 0x3) << 18) 391 #define ESDCFG_TWTR (1 << 20) 392 #define ESDCFG_TXP(x) (((x) & 0x3) << 21) 393 394 #define ESDMISC_RST (1 << 1) 395 #define ESDMISC_MDDREN (1 << 2) 396 #define ESDMISC_MDDR_DL_RST (1 << 3) 397 #define ESDMISC_MDDR_MDIS (1 << 4) 398 #define ESDMISC_LHD (1 << 5) 399 #define ESDMISC_MA10_SHARE (1 << 6) 400 #define ESDMISC_SDRAM_RDY (1 << 31) 401 402 #define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) 403 #define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) 404 #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) 405 #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) 406 #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) 407 #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) 408 #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) 409 #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) 410 #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) 411 412 #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) 413 #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) 414 #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) 415 #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) 416 #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) 417 #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) 418 #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) 419 #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) 420 #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) 421 #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) 422 #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) 423 #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) 424 #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) 425 #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) 426 #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) 427 #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) 428 #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) 429 #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) 430 431 #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) 432 #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) 433 #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) 434 #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) 435 #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) 436 #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) 437 #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) 438 #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) 439 #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) 440 #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) 441 #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) 442 #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) 443 #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) 444 #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) 445 #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) 446 #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 447 #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 448 #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 449 #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 450 #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 451 #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 452 #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 453 #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 454 #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 455 #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 456 #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 457 #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 458 #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) 459 #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) 460 #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) 461 #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) 462 463 /* Clocksource Bitfields */ 464 #define TCTL_SWR (1 << 15) /* Software reset */ 465 #define TCTL_FRR (1 << 8) /* Freerun / restart */ 466 #define TCTL_CAP (3 << 6) /* Capture Edge */ 467 #define TCTL_OM (1 << 5) /* output mode */ 468 #define TCTL_IRQEN (1 << 4) /* interrupt enable */ 469 #define TCTL_CLKSOURCE 1 /* Clock source bit position */ 470 #define TCTL_TEN 1 /* Timer enable */ 471 #define TPRER_PRES 0xff /* Prescale */ 472 #define TSTAT_CAPT (1 << 1) /* Capture event */ 473 #define TSTAT_COMP 1 /* Compare event */ 474 475 #define GPIO_PIN_MASK 0x1f 476 477 #define GPIO_PORT_SHIFT 5 478 #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) 479 480 #define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) 481 #define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) 482 #define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) 483 #define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) 484 #define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) 485 #define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) 486 487 #define GPIO_OUT (1 << 8) 488 #define GPIO_IN (0 << 8) 489 #define GPIO_PUEN (1 << 9) 490 491 #define GPIO_PF (1 << 10) 492 #define GPIO_AF (1 << 11) 493 494 #define GPIO_OCR_SHIFT 12 495 #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) 496 #define GPIO_AIN (0 << GPIO_OCR_SHIFT) 497 #define GPIO_BIN (1 << GPIO_OCR_SHIFT) 498 #define GPIO_CIN (2 << GPIO_OCR_SHIFT) 499 #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) 500 501 #define GPIO_AOUT_SHIFT 14 502 #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) 503 #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) 504 #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) 505 #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) 506 #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) 507 508 #define GPIO_BOUT_SHIFT 16 509 #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) 510 #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) 511 #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) 512 #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) 513 #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) 514 515 #define IIM_STAT_BUSY (1 << 7) 516 #define IIM_STAT_PRGD (1 << 1) 517 #define IIM_STAT_SNSD (1 << 0) 518 #define IIM_ERR_PRGE (1 << 7) 519 #define IIM_ERR_WPE (1 << 6) 520 #define IIM_ERR_OPE (1 << 5) 521 #define IIM_ERR_RPE (1 << 4) 522 #define IIM_ERR_WLRE (1 << 3) 523 #define IIM_ERR_SNSE (1 << 2) 524 #define IIM_ERR_PARITYE (1 << 1) 525 526 #endif /* _IMX_REGS_H */ 527