1 /*
2  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3  * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #ifndef _IMX_REGS_H
25 #define _IMX_REGS_H
26 
27 #ifndef __ASSEMBLY__
28 
29 extern void imx_gpio_mode (int gpio_mode);
30 
31 #ifdef CONFIG_MXC_UART
32 extern void mx27_uart_init_pins(void);
33 #endif /* CONFIG_MXC_UART */
34 
35 #ifdef CONFIG_FEC_MXC
36 extern void mx27_fec_init_pins(void);
37 #endif /* CONFIG_FEC_MXC */
38 
39 #ifdef CONFIG_MXC_MMC
40 extern void mx27_sd1_init_pins(void);
41 extern void mx27_sd2_init_pins(void);
42 #endif /* CONFIG_MXC_MMC */
43 
44 /* AIPI */
45 struct aipi_regs {
46 	u32 psr0;
47 	u32 psr1;
48 };
49 
50 /* System Control */
51 struct system_control_regs {
52 	u32 res[5];
53 	u32 fmcr;
54 	u32 gpcr;
55 	u32 wbcr;
56 	u32 dscr1;
57 	u32 dscr2;
58 	u32 dscr3;
59 	u32 dscr4;
60 	u32 dscr5;
61 	u32 dscr6;
62 	u32 dscr7;
63 	u32 dscr8;
64 	u32 dscr9;
65 	u32 dscr10;
66 	u32 dscr11;
67 	u32 dscr12;
68 	u32 dscr13;
69 	u32 pscr;
70 	u32 pmcr;
71 	u32 res1;
72 	u32 dcvr0;
73 	u32 dcvr1;
74 	u32 dcvr2;
75 	u32 dcvr3;
76 };
77 
78 /* Chip Select Registers */
79 struct weim_regs {
80 	u32 cs0u;	/* Chip Select 0 Upper Register */
81 	u32 cs0l;	/* Chip Select 0 Lower Register */
82 	u32 cs0a;	/* Chip Select 0 Addition Register */
83 	u32 pad0;
84 	u32 cs1u;	/* Chip Select 1 Upper Register */
85 	u32 cs1l;	/* Chip Select 1 Lower Register */
86 	u32 cs1a;	/* Chip Select 1 Addition Register */
87 	u32 pad1;
88 	u32 cs2u;	/* Chip Select 2 Upper Register */
89 	u32 cs2l;	/* Chip Select 2 Lower Register */
90 	u32 cs2a;	/* Chip Select 2 Addition Register */
91 	u32 pad2;
92 	u32 cs3u;	/* Chip Select 3 Upper Register */
93 	u32 cs3l;	/* Chip Select 3 Lower Register */
94 	u32 cs3a;	/* Chip Select 3 Addition Register */
95 	u32 pad3;
96 	u32 cs4u;	/* Chip Select 4 Upper Register */
97 	u32 cs4l;	/* Chip Select 4 Lower Register */
98 	u32 cs4a;	/* Chip Select 4 Addition Register */
99 	u32 pad4;
100 	u32 cs5u;	/* Chip Select 5 Upper Register */
101 	u32 cs5l;	/* Chip Select 5 Lower Register */
102 	u32 cs5a;	/* Chip Select 5 Addition Register */
103 	u32 pad5;
104 	u32 eim;	/* WEIM Configuration Register */
105 };
106 
107 /* SDRAM Controller registers */
108 struct esdramc_regs {
109 /* Enhanced SDRAM Control Register 0 */
110 	u32 esdctl0;
111 /* Enhanced SDRAM Configuration Register 0 */
112 	u32 esdcfg0;
113 /* Enhanced SDRAM Control Register 1 */
114 	u32 esdctl1;
115 /* Enhanced SDRAM Configuration Register 1 */
116 	u32 esdcfg1;
117 /* Enhanced SDRAM Miscellanious Register */
118 	u32 esdmisc;
119 };
120 
121 /* Watchdog Registers*/
122 struct wdog_regs {
123 	u32 wcr;
124 	u32 wsr;
125 	u32 wstr;
126 };
127 
128 /* PLL registers */
129 struct pll_regs {
130 	u32 cscr;	/* Clock Source Control Register */
131 	u32 mpctl0;	/* MCU PLL Control Register 0 */
132 	u32 mpctl1;	/* MCU PLL Control Register 1 */
133 	u32 spctl0;	/* System PLL Control Register 0 */
134 	u32 spctl1;	/* System PLL Control Register 1 */
135 	u32 osc26mctl;	/* Oscillator 26M Register */
136 	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
137 	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
138 	u32 pccr0;	/* Peripheral Clock Control Register 0 */
139 	u32 pccr1;	/* Peripheral Clock Control Register 1 */
140 	u32 ccsr;	/* Clock Control Status Register */
141 };
142 
143 /*
144  * Definitions for the clocksource registers
145  */
146 struct gpt_regs {
147 	u32 gpt_tctl;
148 	u32 gpt_tprer;
149 	u32 gpt_tcmp;
150 	u32 gpt_tcr;
151 	u32 gpt_tcn;
152 	u32 gpt_tstat;
153 };
154 
155 /*
156  *  GPIO Module and I/O Multiplexer
157  */
158 #define PORTA 0
159 #define PORTB 1
160 #define PORTC 2
161 #define PORTD 3
162 #define PORTE 4
163 #define PORTF 5
164 
165 struct gpio_regs {
166 	struct {
167 		u32 ddir;
168 		u32 ocr1;
169 		u32 ocr2;
170 		u32 iconfa1;
171 		u32 iconfa2;
172 		u32 iconfb1;
173 		u32 iconfb2;
174 		u32 dr;
175 		u32 gius;
176 		u32 ssr;
177 		u32 icr1;
178 		u32 icr2;
179 		u32 imr;
180 		u32 isr;
181 		u32 gpr;
182 		u32 swr;
183 		u32 puen;
184 		u32 res[0x2f];
185 	} port[6];
186 };
187 
188 /* IIM Control Registers */
189 struct iim_regs {
190 	u32 iim_stat;
191 	u32 iim_statm;
192 	u32 iim_err;
193 	u32 iim_emask;
194 	u32 iim_fctl;
195 	u32 iim_ua;
196 	u32 iim_la;
197 	u32 iim_sdat;
198 	u32 iim_prev;
199 	u32 iim_srev;
200 	u32 iim_prog_p;
201 	u32 iim_scs0;
202 	u32 iim_scs1;
203 	u32 iim_scs2;
204 	u32 iim_scs3;
205 	u32 res[0x1F0];
206 	u32 iim_bank_area0[0x100];
207 };
208 #endif
209 
210 #define IMX_IO_BASE		0x10000000
211 
212 #define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
213 #define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
214 #define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
215 #define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
216 #define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
217 #define IMX_UART1_BASE		(0x0a000 + IMX_IO_BASE)
218 #define IMX_UART2_BASE		(0x0b000 + IMX_IO_BASE)
219 #define IMX_UART3_BASE		(0x0c000 + IMX_IO_BASE)
220 #define IMX_UART4_BASE		(0x0d000 + IMX_IO_BASE)
221 #define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
222 #define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
223 #define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
224 #define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
225 #define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
226 #define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
227 #define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
228 #define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
229 #define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
230 #define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
231 #define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
232 #define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
233 #define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
234 
235 #define IMX_ESD_BASE		(0xD8001000)
236 #define IMX_WEIM_BASE		(0xD8002000)
237 
238 /* FMCR System Control bit definition*/
239 #define UART4_RXD_CTL	(1 << 25)
240 #define UART4_RTS_CTL	(1 << 24)
241 #define KP_COL6_CTL	(1 << 18)
242 #define KP_ROW7_CTL	(1 << 17)
243 #define KP_ROW6_CTL	(1 << 16)
244 #define PC_WAIT_B_CTL	(1 << 14)
245 #define PC_READY_CTL	(1 << 13)
246 #define PC_VS1_CTL	(1 << 12)
247 #define PC_VS2_CTL	(1 << 11)
248 #define PC_BVD1_CTL	(1 << 10)
249 #define PC_BVD2_CTL	(1 << 9)
250 #define IOS16_CTL	(1 << 8)
251 #define NF_FMS		(1 << 5)
252 #define NF_16BIT_SEL	(1 << 4)
253 #define SLCDC_SEL	(1 << 2)
254 #define SDCS1_SEL	(1 << 1)
255 #define SDCS0_SEL	(1 << 0)
256 
257 
258 /* important definition of some bits of WCR */
259 #define WCR_WDE 0x04
260 
261 #define CSCR_MPEN		(1 << 0)
262 #define CSCR_SPEN		(1 << 1)
263 #define CSCR_FPM_EN		(1 << 2)
264 #define CSCR_OSC26M_DIS		(1 << 3)
265 #define CSCR_OSC26M_DIV1P5	(1 << 4)
266 #define CSCR_AHB_DIV
267 #define CSCR_ARM_DIV
268 #define CSCR_ARM_SRC_MPLL	(1 << 15)
269 #define CSCR_MCU_SEL		(1 << 16)
270 #define CSCR_SP_SEL		(1 << 17)
271 #define CSCR_MPLL_RESTART	(1 << 18)
272 #define CSCR_SPLL_RESTART	(1 << 19)
273 #define CSCR_MSHC_SEL		(1 << 20)
274 #define CSCR_H264_SEL		(1 << 21)
275 #define CSCR_SSI1_SEL		(1 << 22)
276 #define CSCR_SSI2_SEL		(1 << 23)
277 #define CSCR_SD_CNT
278 #define CSCR_USB_DIV
279 #define CSCR_UPDATE_DIS		(1 << 31)
280 
281 #define MPCTL1_BRMO		(1 << 6)
282 #define MPCTL1_LF		(1 << 15)
283 
284 #define PCCR0_SSI2_EN	(1 << 0)
285 #define PCCR0_SSI1_EN	(1 << 1)
286 #define PCCR0_SLCDC_EN	(1 << 2)
287 #define PCCR0_SDHC3_EN	(1 << 3)
288 #define PCCR0_SDHC2_EN	(1 << 4)
289 #define PCCR0_SDHC1_EN	(1 << 5)
290 #define PCCR0_SDC_EN	(1 << 6)
291 #define PCCR0_SAHARA_EN	(1 << 7)
292 #define PCCR0_RTIC_EN	(1 << 8)
293 #define PCCR0_RTC_EN	(1 << 9)
294 #define PCCR0_PWM_EN	(1 << 11)
295 #define PCCR0_OWIRE_EN	(1 << 12)
296 #define PCCR0_MSHC_EN	(1 << 13)
297 #define PCCR0_LCDC_EN	(1 << 14)
298 #define PCCR0_KPP_EN	(1 << 15)
299 #define PCCR0_IIM_EN	(1 << 16)
300 #define PCCR0_I2C2_EN	(1 << 17)
301 #define PCCR0_I2C1_EN	(1 << 18)
302 #define PCCR0_GPT6_EN	(1 << 19)
303 #define PCCR0_GPT5_EN	(1 << 20)
304 #define PCCR0_GPT4_EN	(1 << 21)
305 #define PCCR0_GPT3_EN	(1 << 22)
306 #define PCCR0_GPT2_EN	(1 << 23)
307 #define PCCR0_GPT1_EN	(1 << 24)
308 #define PCCR0_GPIO_EN	(1 << 25)
309 #define PCCR0_FEC_EN	(1 << 26)
310 #define PCCR0_EMMA_EN	(1 << 27)
311 #define PCCR0_DMA_EN	(1 << 28)
312 #define PCCR0_CSPI3_EN	(1 << 29)
313 #define PCCR0_CSPI2_EN	(1 << 30)
314 #define PCCR0_CSPI1_EN	(1 << 31)
315 
316 #define PCCR1_MSHC_BAUDEN	(1 << 2)
317 #define PCCR1_NFC_BAUDEN	(1 << 3)
318 #define PCCR1_SSI2_BAUDEN	(1 << 4)
319 #define PCCR1_SSI1_BAUDEN	(1 << 5)
320 #define PCCR1_H264_BAUDEN	(1 << 6)
321 #define PCCR1_PERCLK4_EN	(1 << 7)
322 #define PCCR1_PERCLK3_EN	(1 << 8)
323 #define PCCR1_PERCLK2_EN	(1 << 9)
324 #define PCCR1_PERCLK1_EN	(1 << 10)
325 #define PCCR1_HCLK_USB		(1 << 11)
326 #define PCCR1_HCLK_SLCDC	(1 << 12)
327 #define PCCR1_HCLK_SAHARA	(1 << 13)
328 #define PCCR1_HCLK_RTIC		(1 << 14)
329 #define PCCR1_HCLK_LCDC		(1 << 15)
330 #define PCCR1_HCLK_H264		(1 << 16)
331 #define PCCR1_HCLK_FEC		(1 << 17)
332 #define PCCR1_HCLK_EMMA		(1 << 18)
333 #define PCCR1_HCLK_EMI		(1 << 19)
334 #define PCCR1_HCLK_DMA		(1 << 20)
335 #define PCCR1_HCLK_CSI		(1 << 21)
336 #define PCCR1_HCLK_BROM		(1 << 22)
337 #define PCCR1_HCLK_ATA		(1 << 23)
338 #define PCCR1_WDT_EN		(1 << 24)
339 #define PCCR1_USB_EN		(1 << 25)
340 #define PCCR1_UART6_EN		(1 << 26)
341 #define PCCR1_UART5_EN		(1 << 27)
342 #define PCCR1_UART4_EN		(1 << 28)
343 #define PCCR1_UART3_EN		(1 << 29)
344 #define PCCR1_UART2_EN		(1 << 30)
345 #define PCCR1_UART1_EN		(1 << 31)
346 
347 /* SDRAM Controller registers bitfields */
348 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
349 #define ESDCTL_BL		(1 << 7)
350 #define ESDCTL_FP		(1 << 8)
351 #define ESDCTL_PWDT(x)		(((x) & 3) << 10)
352 #define ESDCTL_SREFR(x)		(((x) & 7) << 13)
353 #define ESDCTL_DSIZ_16_UPPER	(0 << 16)
354 #define ESDCTL_DSIZ_16_LOWER	(1 << 16)
355 #define ESDCTL_DSIZ_32		(2 << 16)
356 #define ESDCTL_COL8		(0 << 20)
357 #define ESDCTL_COL9		(1 << 20)
358 #define ESDCTL_COL10		(2 << 20)
359 #define ESDCTL_ROW11		(0 << 24)
360 #define ESDCTL_ROW12		(1 << 24)
361 #define ESDCTL_ROW13		(2 << 24)
362 #define ESDCTL_ROW14		(3 << 24)
363 #define ESDCTL_ROW15		(4 << 24)
364 #define ESDCTL_SP		(1 << 27)
365 #define ESDCTL_SMODE_NORMAL	(0 << 28)
366 #define ESDCTL_SMODE_PRECHARGE	(1 << 28)
367 #define ESDCTL_SMODE_AUTO_REF	(2 << 28)
368 #define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
369 #define ESDCTL_SMODE_MAN_REF	(4 << 28)
370 #define ESDCTL_SDE		(1 << 31)
371 
372 #define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
373 #define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
374 #define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
375 #define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
376 #define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
377 #define ESDCFG_TWR		(1 << 15)
378 #define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
379 #define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
380 #define ESDCFG_TWTR		(1 << 20)
381 #define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
382 
383 #define ESDMISC_RST		(1 << 1)
384 #define ESDMISC_MDDREN		(1 << 2)
385 #define ESDMISC_MDDR_DL_RST	(1 << 3)
386 #define ESDMISC_MDDR_MDIS	(1 << 4)
387 #define ESDMISC_LHD		(1 << 5)
388 #define ESDMISC_MA10_SHARE	(1 << 6)
389 #define ESDMISC_SDRAM_RDY	(1 << 31)
390 
391 #define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
392 #define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
393 #define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
394 #define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
395 #define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
396 #define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
397 #define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
398 #define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
399 #define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
400 
401 #define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
402 #define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
403 #define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
404 #define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
405 #define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
406 #define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
407 #define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
408 #define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
409 #define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
410 #define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
411 #define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
412 #define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
413 #define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
414 #define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
415 #define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
416 #define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
417 #define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
418 #define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
419 
420 #define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
421 #define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
422 #define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
423 #define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
424 #define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
425 #define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
426 #define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
427 #define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
428 #define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
429 #define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
430 #define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
431 #define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
432 #define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
433 #define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
434 #define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
435 #define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
436 #define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
437 #define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
438 #define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
439 #define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
440 #define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
441 #define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
442 #define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
443 #define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
444 #define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
445 #define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
446 #define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
447 #define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
448 #define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
449 #define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
450 #define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
451 
452 /* Clocksource Bitfields */
453 #define TCTL_SWR	(1 << 15)	/* Software reset */
454 #define TCTL_FRR	(1 << 8)	/* Freerun / restart */
455 #define TCTL_CAP	(3 << 6)	/* Capture Edge */
456 #define TCTL_OM		(1 << 5)	/* output mode */
457 #define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
458 #define TCTL_CLKSOURCE	1		/* Clock source bit position */
459 #define TCTL_TEN	1		/* Timer enable */
460 #define TPRER_PRES	0xff		/* Prescale */
461 #define TSTAT_CAPT	(1 << 1)	/* Capture event */
462 #define TSTAT_COMP	1		/* Compare event */
463 
464 #define GPIO_PIN_MASK	0x1f
465 
466 #define GPIO_PORT_SHIFT	5
467 #define GPIO_PORT_MASK	(0x7 << GPIO_PORT_SHIFT)
468 
469 #define GPIO_PORTA	(PORTA << GPIO_PORT_SHIFT)
470 #define GPIO_PORTB	(PORTB << GPIO_PORT_SHIFT)
471 #define GPIO_PORTC	(PORTC << GPIO_PORT_SHIFT)
472 #define GPIO_PORTD	(PORTD << GPIO_PORT_SHIFT)
473 #define GPIO_PORTE	(PORTE << GPIO_PORT_SHIFT)
474 #define GPIO_PORTF	(PORTF << GPIO_PORT_SHIFT)
475 
476 #define GPIO_OUT	(1 << 8)
477 #define GPIO_IN		(0 << 8)
478 #define GPIO_PUEN	(1 << 9)
479 
480 #define GPIO_PF		(1 << 10)
481 #define GPIO_AF		(1 << 11)
482 
483 #define GPIO_OCR_SHIFT	12
484 #define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
485 #define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
486 #define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
487 #define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
488 #define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)
489 
490 #define GPIO_AOUT_SHIFT	14
491 #define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
492 #define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
493 #define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
494 #define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
495 #define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)
496 
497 #define GPIO_BOUT_SHIFT	16
498 #define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
499 #define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
500 #define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
501 #define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
502 #define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
503 
504 #define IIM_STAT_BUSY	(1 << 7)
505 #define IIM_STAT_PRGD	(1 << 1)
506 #define IIM_STAT_SNSD	(1 << 0)
507 #define IIM_ERR_PRGE	(1 << 7)
508 #define IIM_ERR_WPE	(1 << 6)
509 #define IIM_ERR_OPE	(1 << 5)
510 #define IIM_ERR_RPE	(1 << 4)
511 #define IIM_ERR_WLRE	(1 << 3)
512 #define IIM_ERR_SNSE	(1 << 2)
513 #define IIM_ERR_PARITYE	(1 << 1)
514 
515 /* Definitions for i.MX27 TO2 */
516 #define IIM0_MAC		5
517 #define IIM0_SCC_KEY		11
518 #define IIM1_SUID		1
519 
520 #endif				/* _IMX_REGS_H */
521