1 /*
2  * Copyright (C) 2009, DENX Software Engineering
3  * Author: John Rigby <jcrigby@gmail.com
4  *
5  *   Based on arch-mx31/mx31-regs.h
6  *	Copyright (C) 2009 Ilya Yanok,
7  *		Emcraft Systems <yanok@emcraft.com>
8  *   and arch-mx27/imx-regs.h
9  *	Copyright (C) 2007 Pengutronix,
10  *		Sascha Hauer <s.hauer@pengutronix.de>
11  *	Copyright (C) 2009 Ilya Yanok,
12  *		Emcraft Systems <yanok@emcraft.com>
13  *
14  * See file CREDITS for list of people who contributed to this
15  * project.
16  *
17  * This program is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU General Public License as
19  * published by the Free Software Foundation; either version 2 of
20  * the License, or (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  * GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License
28  * along with this program; if not, write to the Free Software
29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30  * MA 02111-1307 USA
31  */
32 
33 #ifndef _IMX_REGS_H
34 #define _IMX_REGS_H
35 
36 #ifndef __ASSEMBLY__
37 
38 #include <asm/types.h>
39 
40 #ifdef CONFIG_FEC_MXC
41 extern void mx25_fec_init_pins(void);
42 #endif
43 
44 /* Clock Control Module (CCM) registers */
45 struct ccm_regs {
46 	u32 mpctl;	/* Core PLL Control */
47 	u32 upctl;	/* USB PLL Control */
48 	u32 cctl;	/* Clock Control */
49 	u32 cgr0;	/* Clock Gating Control 0 */
50 	u32 cgr1;	/* Clock Gating Control 1 */
51 	u32 cgr2;	/* Clock Gating Control 2 */
52 	u32 pcdr[4];	/* PER Clock Dividers */
53 	u32 rcsr;	/* CCM Status */
54 	u32 crdr;	/* CCM Reset and Debug */
55 	u32 dcvr0;	/* DPTC Comparator Value 0 */
56 	u32 dcvr1;	/* DPTC Comparator Value 1 */
57 	u32 dcvr2;	/* DPTC Comparator Value 2 */
58 	u32 dcvr3;	/* DPTC Comparator Value 3 */
59 	u32 ltr0;	/* Load Tracking 0 */
60 	u32 ltr1;	/* Load Tracking 1 */
61 	u32 ltr2;	/* Load Tracking 2 */
62 	u32 ltr3;	/* Load Tracking 3 */
63 	u32 ltbr0;	/* Load Tracking Buffer 0 */
64 	u32 ltbr1;	/* Load Tracking Buffer 1 */
65 	u32 pcmr0;	/* Power Management Control 0 */
66 	u32 pcmr1;	/* Power Management Control 1 */
67 	u32 pcmr2;	/* Power Management Control 2 */
68 	u32 mcr;	/* Miscellaneous Control */
69 	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
70 	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
71 };
72 
73 /* Enhanced SDRAM Controller (ESDRAMC) registers */
74 struct esdramc_regs {
75 	u32 ctl0; 	/* control 0 */
76 	u32 cfg0; 	/* configuration 0 */
77 	u32 ctl1; 	/* control 1 */
78 	u32 cfg1; 	/* configuration 1 */
79 	u32 misc; 	/* miscellaneous */
80 	u32 pad[3];
81 	u32 cdly1;	/* Delay Line 1 configuration debug */
82 	u32 cdly2;	/* delay line 2 configuration debug */
83 	u32 cdly3;	/* delay line 3 configuration debug */
84 	u32 cdly4;	/* delay line 4 configuration debug */
85 	u32 cdly5;	/* delay line 5 configuration debug */
86 	u32 cdlyl;	/* delay line cycle length debug */
87 };
88 
89 /* General Purpose Timer (GPT) registers */
90 struct gpt_regs {
91 	u32 ctrl;   	/* control */
92 	u32 pre;    	/* prescaler */
93 	u32 stat;   	/* status */
94 	u32 intr;   	/* interrupt */
95 	u32 cmp[3]; 	/* output compare 1-3 */
96 	u32 capt[2];	/* input capture 1-2 */
97 	u32 counter;	/* counter */
98 };
99 
100 /* Watchdog Timer (WDOG) registers */
101 struct wdog_regs {
102 	u16 wcr;	/* Control */
103 	u16 wsr;	/* Service */
104 	u16 wrsr;	/* Reset Status */
105 	u16 wicr;	/* Interrupt Control */
106 	u16 wmcr;	/* Misc Control */
107 };
108 
109 /* IIM control registers */
110 struct iim_regs {
111 	u32 iim_stat;
112 	u32 iim_statm;
113 	u32 iim_err;
114 	u32 iim_emask;
115 	u32 iim_fctl;
116 	u32 iim_ua;
117 	u32 iim_la;
118 	u32 iim_sdat;
119 	u32 iim_prev;
120 	u32 iim_srev;
121 	u32 iim_prog_p;
122 	u32 res1[0x1f5];
123 	struct fuse_bank {
124 		u32 fuse_regs[0x20];
125 		u32 fuse_rsvd[0xe0];
126 	} bank[3];
127 };
128 
129 struct fuse_bank0_regs {
130 	u32 fuse0_25[0x1a];
131 	u32 mac_addr[6];
132 };
133 
134 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
135 struct max_regs {
136 	u32 mpr0;
137 	u32 pad00[3];
138 	u32 sgpcr0;
139 	u32 pad01[59];
140 	u32 mpr1;
141 	u32 pad02[3];
142 	u32 sgpcr1;
143 	u32 pad03[59];
144 	u32 mpr2;
145 	u32 pad04[3];
146 	u32 sgpcr2;
147 	u32 pad05[59];
148 	u32 mpr3;
149 	u32 pad06[3];
150 	u32 sgpcr3;
151 	u32 pad07[59];
152 	u32 mpr4;
153 	u32 pad08[3];
154 	u32 sgpcr4;
155 	u32 pad09[251];
156 	u32 mgpcr0;
157 	u32 pad10[63];
158 	u32 mgpcr1;
159 	u32 pad11[63];
160 	u32 mgpcr2;
161 	u32 pad12[63];
162 	u32 mgpcr3;
163 	u32 pad13[63];
164 	u32 mgpcr4;
165 };
166 
167 /* AHB <-> IP-Bus Interface (AIPS) */
168 struct aips_regs {
169 	u32 mpr_0_7;
170 	u32 mpr_8_15;
171 };
172 
173 #endif
174 
175 /* AIPS 1 */
176 #define IMX_AIPS1_BASE		(0x43F00000)
177 #define IMX_MAX_BASE		(0x43F04000)
178 #define IMX_CLKCTL_BASE		(0x43F08000)
179 #define IMX_ETB_SLOT4_BASE	(0x43F0C000)
180 #define IMX_ETB_SLOT5_BASE	(0x43F10000)
181 #define IMX_ECT_CTIO_BASE	(0x43F18000)
182 #define IMX_I2C_BASE		(0x43F80000)
183 #define IMX_I2C3_BASE		(0x43F84000)
184 #define IMX_CAN1_BASE		(0x43F88000)
185 #define IMX_CAN2_BASE		(0x43F8C000)
186 #define UART1_BASE		(0x43F90000)
187 #define UART2_BASE		(0x43F94000)
188 #define IMX_I2C2_BASE		(0x43F98000)
189 #define IMX_OWIRE_BASE		(0x43F9C000)
190 #define IMX_CSPI1_BASE		(0x43FA4000)
191 #define IMX_KPP_BASE		(0x43FA8000)
192 #define IMX_IOPADMUX_BASE	(0x43FAC000)
193 #define IMX_IOPADCTL_BASE	(0x43FAC22C)
194 #define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
195 #define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
196 #define IMX_AUDMUX_BASE		(0x43FB0000)
197 #define IMX_ECT_IP1_BASE	(0x43FB8000)
198 #define IMX_ECT_IP2_BASE	(0x43FBC000)
199 
200 /* SPBA */
201 #define IMX_SPBA_BASE		(0x50000000)
202 #define IMX_CSPI3_BASE		(0x50004000)
203 #define UART4_BASE		(0x50008000)
204 #define UART3_BASE		(0x5000C000)
205 #define IMX_CSPI2_BASE		(0x50010000)
206 #define IMX_SSI2_BASE		(0x50014000)
207 #define IMX_ESAI_BASE		(0x50018000)
208 #define IMX_ATA_DMA_BASE	(0x50020000)
209 #define IMX_SIM1_BASE		(0x50024000)
210 #define IMX_SIM2_BASE		(0x50028000)
211 #define UART5_BASE		(0x5002C000)
212 #define IMX_TSC_BASE		(0x50030000)
213 #define IMX_SSI1_BASE		(0x50034000)
214 #define IMX_FEC_BASE		(0x50038000)
215 #define IMX_SPBA_CTRL_BASE	(0x5003C000)
216 
217 /* AIPS 2 */
218 #define IMX_AIPS2_BASE		(0x53F00000)
219 #define IMX_CCM_BASE		(0x53F80000)
220 #define IMX_GPT4_BASE		(0x53F84000)
221 #define IMX_GPT3_BASE		(0x53F88000)
222 #define IMX_GPT2_BASE		(0x53F8C000)
223 #define IMX_GPT1_BASE		(0x53F90000)
224 #define IMX_EPIT1_BASE		(0x53F94000)
225 #define IMX_EPIT2_BASE		(0x53F98000)
226 #define IMX_GPIO4_BASE		(0x53F9C000)
227 #define IMX_PWM2_BASE		(0x53FA0000)
228 #define IMX_GPIO3_BASE		(0x53FA4000)
229 #define IMX_PWM3_BASE		(0x53FA8000)
230 #define IMX_SCC_BASE		(0x53FAC000)
231 #define IMX_SCM_BASE		(0x53FAE000)
232 #define IMX_SMN_BASE		(0x53FAF000)
233 #define IMX_RNGD_BASE		(0x53FB0000)
234 #define IMX_MMC_SDHC1_BASE	(0x53FB4000)
235 #define IMX_MMC_SDHC2_BASE	(0x53FB8000)
236 #define IMX_LCDC_BASE		(0x53FBC000)
237 #define IMX_SLCDC_BASE		(0x53FC0000)
238 #define IMX_PWM4_BASE		(0x53FC8000)
239 #define IMX_GPIO1_BASE		(0x53FCC000)
240 #define IMX_GPIO2_BASE		(0x53FD0000)
241 #define IMX_SDMA_BASE		(0x53FD4000)
242 #define IMX_WDT_BASE		(0x53FDC000)
243 #define IMX_PWM1_BASE		(0x53FE0000)
244 #define IMX_RTIC_BASE		(0x53FEC000)
245 #define IMX_IIM_BASE		(0x53FF0000)
246 #define IMX_USB_BASE		(0x53FF4000)
247 #define IMX_CSI_BASE		(0x53FF8000)
248 #define IMX_DRYICE_BASE		(0x53FFC000)
249 
250 #define IMX_ARM926_ROMPATCH	(0x60000000)
251 #define IMX_ARM926_ASIC		(0x68000000)
252 
253 /* 128K Internal Static RAM */
254 #define IMX_RAM_BASE		(0x78000000)
255 
256 /* SDRAM BANKS */
257 #define IMX_SDRAM_BANK0_BASE	(0x80000000)
258 #define IMX_SDRAM_BANK1_BASE	(0x90000000)
259 
260 #define IMX_WEIM_CS0		(0xA0000000)
261 #define IMX_WEIM_CS1		(0xA8000000)
262 #define IMX_WEIM_CS2		(0xB0000000)
263 #define IMX_WEIM_CS3		(0xB2000000)
264 #define IMX_WEIM_CS4		(0xB4000000)
265 #define IMX_ESDRAMC_BASE	(0xB8001000)
266 #define IMX_WEIM_CTRL_BASE	(0xB8002000)
267 #define IMX_M3IF_CTRL_BASE	(0xB8003000)
268 #define IMX_EMI_CTRL_BASE	(0xB8004000)
269 
270 /* NAND Flash Controller */
271 #define IMX_NFC_BASE		(0xBB000000)
272 #define NFC_BASE_ADDR		IMX_NFC_BASE
273 
274 /* CCM bitfields */
275 #define CCM_PLL_MFI_SHIFT	10
276 #define CCM_PLL_MFI_MASK	0xf
277 #define CCM_PLL_MFN_SHIFT	0
278 #define CCM_PLL_MFN_MASK	0x3ff
279 #define CCM_PLL_MFD_SHIFT	16
280 #define CCM_PLL_MFD_MASK	0x3ff
281 #define CCM_PLL_PD_SHIFT	26
282 #define CCM_PLL_PD_MASK		0xf
283 #define CCM_CCTL_ARM_DIV_SHIFT	30
284 #define CCM_CCTL_ARM_DIV_MASK	3
285 #define CCM_CCTL_AHB_DIV_SHIFT	28
286 #define CCM_CCTL_AHB_DIV_MASK	3
287 #define CCM_CCTL_ARM_SRC	(1 << 14)
288 #define CCM_CGR1_GPT1		(1 << 19)
289 #define CCM_PERCLK_REG(clk)	(clk / 4)
290 #define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
291 #define CCM_PERCLK_MASK		0x3f
292 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
293 #define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
294 
295 /* ESDRAM Controller register bitfields */
296 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
297 #define ESDCTL_BL		(1 << 7)
298 #define ESDCTL_FP		(1 << 8)
299 #define ESDCTL_PWDT(x)		(((x) & 3) << 10)
300 #define ESDCTL_SREFR(x)		(((x) & 7) << 13)
301 #define ESDCTL_DSIZ_16_UPPER	(0 << 16)
302 #define ESDCTL_DSIZ_16_LOWER	(1 << 16)
303 #define ESDCTL_DSIZ_32		(2 << 16)
304 #define ESDCTL_COL8		(0 << 20)
305 #define ESDCTL_COL9		(1 << 20)
306 #define ESDCTL_COL10		(2 << 20)
307 #define ESDCTL_ROW11		(0 << 24)
308 #define ESDCTL_ROW12		(1 << 24)
309 #define ESDCTL_ROW13		(2 << 24)
310 #define ESDCTL_ROW14		(3 << 24)
311 #define ESDCTL_ROW15		(4 << 24)
312 #define ESDCTL_SP		(1 << 27)
313 #define ESDCTL_SMODE_NORMAL	(0 << 28)
314 #define ESDCTL_SMODE_PRECHARGE	(1 << 28)
315 #define ESDCTL_SMODE_AUTO_REF	(2 << 28)
316 #define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
317 #define ESDCTL_SMODE_MAN_REF	(4 << 28)
318 #define ESDCTL_SDE		(1 << 31)
319 
320 #define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
321 #define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
322 #define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
323 #define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
324 #define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
325 #define ESDCFG_TWR		(1 << 15)
326 #define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
327 #define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
328 #define ESDCFG_TWTR		(1 << 20)
329 #define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
330 
331 #define ESDMISC_RST		(1 << 1)
332 #define ESDMISC_MDDREN		(1 << 2)
333 #define ESDMISC_MDDR_DL_RST	(1 << 3)
334 #define ESDMISC_MDDR_MDIS	(1 << 4)
335 #define ESDMISC_LHD		(1 << 5)
336 #define ESDMISC_MA10_SHARE	(1 << 6)
337 #define ESDMISC_SDRAM_RDY	(1 << 31)
338 
339 /* GPT bits */
340 #define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
341 #define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
342 #define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
343 #define GPT_CTRL_TEN		1		/* Timer enable	*/
344 
345 /* WDOG enable */
346 #define WCR_WDE 		0x04
347 #define WSR_UNLOCK1		0x5555
348 #define WSR_UNLOCK2		0xAAAA
349 
350 /* Names used in GPIO driver */
351 #define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
352 #define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
353 #define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
354 #define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
355 
356 #define CHIP_REV_1_0		0x10
357 #define CHIP_REV_1_1		0x11
358 
359 #endif				/* _IMX_REGS_H */
360