1 /*
2  * Copyright (C) 2009, DENX Software Engineering
3  * Author: John Rigby <jcrigby@gmail.com
4  *
5  *   Based on arch-mx31/mx31-regs.h
6  *	Copyright (C) 2009 Ilya Yanok,
7  *		Emcraft Systems <yanok@emcraft.com>
8  *   and arch-mx27/imx-regs.h
9  *	Copyright (C) 2007 Pengutronix,
10  *		Sascha Hauer <s.hauer@pengutronix.de>
11  *	Copyright (C) 2009 Ilya Yanok,
12  *		Emcraft Systems <yanok@emcraft.com>
13  *
14  * See file CREDITS for list of people who contributed to this
15  * project.
16  *
17  * This program is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU General Public License as
19  * published by the Free Software Foundation; either version 2 of
20  * the License, or (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  * GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License
28  * along with this program; if not, write to the Free Software
29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30  * MA 02111-1307 USA
31  */
32 
33 #ifndef _IMX_REGS_H
34 #define _IMX_REGS_H
35 
36 #ifndef __ASSEMBLY__
37 #ifdef CONFIG_FEC_MXC
38 extern void mx25_fec_init_pins(void);
39 extern void imx_get_mac_from_fuse(unsigned char *mac);
40 #endif
41 
42 /* Clock Control Module (CCM) registers */
43 struct ccm_regs {
44 	u32 mpctl;	/* Core PLL Control */
45 	u32 upctl;	/* USB PLL Control */
46 	u32 cctl;	/* Clock Control */
47 	u32 cgr0;	/* Clock Gating Control 0 */
48 	u32 cgr1;	/* Clock Gating Control 1 */
49 	u32 cgr2;	/* Clock Gating Control 2 */
50 	u32 pcdr[4];	/* PER Clock Dividers */
51 	u32 rcsr;	/* CCM Status */
52 	u32 crdr;	/* CCM Reset and Debug */
53 	u32 dcvr0;	/* DPTC Comparator Value 0 */
54 	u32 dcvr1;	/* DPTC Comparator Value 1 */
55 	u32 dcvr2;	/* DPTC Comparator Value 2 */
56 	u32 dcvr3;	/* DPTC Comparator Value 3 */
57 	u32 ltr0;	/* Load Tracking 0 */
58 	u32 ltr1;	/* Load Tracking 1 */
59 	u32 ltr2;	/* Load Tracking 2 */
60 	u32 ltr3;	/* Load Tracking 3 */
61 	u32 ltbr0;	/* Load Tracking Buffer 0 */
62 	u32 ltbr1;	/* Load Tracking Buffer 1 */
63 	u32 pcmr0;	/* Power Management Control 0 */
64 	u32 pcmr1;	/* Power Management Control 1 */
65 	u32 pcmr2;	/* Power Management Control 2 */
66 	u32 mcr;	/* Miscellaneous Control */
67 	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
68 	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
69 };
70 
71 /* Enhanced SDRAM Controller (ESDRAMC) registers */
72 struct esdramc_regs {
73 	u32 ctl0; 	/* control 0 */
74 	u32 cfg0; 	/* configuration 0 */
75 	u32 ctl1; 	/* control 1 */
76 	u32 cfg1; 	/* configuration 1 */
77 	u32 misc; 	/* miscellaneous */
78 	u32 pad[3];
79 	u32 cdly1;	/* Delay Line 1 configuration debug */
80 	u32 cdly2;	/* delay line 2 configuration debug */
81 	u32 cdly3;	/* delay line 3 configuration debug */
82 	u32 cdly4;	/* delay line 4 configuration debug */
83 	u32 cdly5;	/* delay line 5 configuration debug */
84 	u32 cdlyl;	/* delay line cycle length debug */
85 };
86 
87 /* GPIO registers */
88 struct gpio_regs {
89 	u32 gpio_dr;	/* data */
90 	u32 gpio_dir;	/* direction */
91 	u32 psr;	/* pad satus */
92 	u32 icr1;	/* interrupt config 1 */
93 	u32 icr2;	/* interrupt config 2 */
94 	u32 imr;	/* interrupt mask */
95 	u32 isr;	/* interrupt status */
96 	u32 edge_sel;	/* edge select */
97 };
98 
99 /* General Purpose Timer (GPT) registers */
100 struct gpt_regs {
101 	u32 ctrl;   	/* control */
102 	u32 pre;    	/* prescaler */
103 	u32 stat;   	/* status */
104 	u32 intr;   	/* interrupt */
105 	u32 cmp[3]; 	/* output compare 1-3 */
106 	u32 capt[2];	/* input capture 1-2 */
107 	u32 counter;	/* counter */
108 };
109 
110 /* Watchdog Timer (WDOG) registers */
111 struct wdog_regs {
112 	u16 wcr;	/* Control */
113 	u16 wsr;	/* Service */
114 	u16 wrsr;	/* Reset Status */
115 	u16 wicr;	/* Interrupt Control */
116 	u16 wmcr;	/* Misc Control */
117 };
118 
119 /* IIM control registers */
120 struct iim_regs {
121 	u32 iim_stat;
122 	u32 iim_statm;
123 	u32 iim_err;
124 	u32 iim_emask;
125 	u32 iim_fctl;
126 	u32 iim_ua;
127 	u32 iim_la;
128 	u32 iim_sdat;
129 	u32 iim_prev;
130 	u32 iim_srev;
131 	u32 iim_prog_p;
132 	u32 res1[0x1f5];
133 	struct fuse_bank {
134 		u32 fuse_regs[0x20];
135 		u32 fuse_rsvd[0xe0];
136 	} bank[3];
137 };
138 
139 struct fuse_bank0_regs {
140 	u32 fuse0_25[0x1a];
141 	u32 mac_addr[6];
142 };
143 
144 /* Multi-Layer AHB Crossbar Switch (MAX) registers */
145 struct max_regs {
146 	u32 mpr0;
147 	u32 pad00[3];
148 	u32 sgpcr0;
149 	u32 pad01[59];
150 	u32 mpr1;
151 	u32 pad02[3];
152 	u32 sgpcr1;
153 	u32 pad03[59];
154 	u32 mpr2;
155 	u32 pad04[3];
156 	u32 sgpcr2;
157 	u32 pad05[59];
158 	u32 mpr3;
159 	u32 pad06[3];
160 	u32 sgpcr3;
161 	u32 pad07[59];
162 	u32 mpr4;
163 	u32 pad08[3];
164 	u32 sgpcr4;
165 	u32 pad09[251];
166 	u32 mgpcr0;
167 	u32 pad10[63];
168 	u32 mgpcr1;
169 	u32 pad11[63];
170 	u32 mgpcr2;
171 	u32 pad12[63];
172 	u32 mgpcr3;
173 	u32 pad13[63];
174 	u32 mgpcr4;
175 };
176 
177 /* AHB <-> IP-Bus Interface (AIPS) */
178 struct aips_regs {
179 	u32 mpr_0_7;
180 	u32 mpr_8_15;
181 };
182 
183 #endif
184 
185 /* AIPS 1 */
186 #define IMX_AIPS1_BASE		(0x43F00000)
187 #define IMX_MAX_BASE		(0x43F04000)
188 #define IMX_CLKCTL_BASE		(0x43F08000)
189 #define IMX_ETB_SLOT4_BASE	(0x43F0C000)
190 #define IMX_ETB_SLOT5_BASE	(0x43F10000)
191 #define IMX_ECT_CTIO_BASE	(0x43F18000)
192 #define IMX_I2C_BASE		(0x43F80000)
193 #define IMX_I2C3_BASE		(0x43F84000)
194 #define IMX_CAN1_BASE		(0x43F88000)
195 #define IMX_CAN2_BASE		(0x43F8C000)
196 #define IMX_UART1_BASE		(0x43F90000)
197 #define IMX_UART2_BASE		(0x43F94000)
198 #define IMX_I2C2_BASE		(0x43F98000)
199 #define IMX_OWIRE_BASE		(0x43F9C000)
200 #define IMX_CSPI1_BASE		(0x43FA4000)
201 #define IMX_KPP_BASE		(0x43FA8000)
202 #define IMX_IOPADMUX_BASE	(0x43FAC000)
203 #define IMX_IOPADCTL_BASE	(0x43FAC22C)
204 #define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
205 #define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
206 #define IMX_AUDMUX_BASE		(0x43FB0000)
207 #define IMX_ECT_IP1_BASE	(0x43FB8000)
208 #define IMX_ECT_IP2_BASE	(0x43FBC000)
209 
210 /* SPBA */
211 #define IMX_SPBA_BASE		(0x50000000)
212 #define IMX_CSPI3_BASE		(0x50004000)
213 #define IMX_UART4_BASE		(0x50008000)
214 #define IMX_UART3_BASE		(0x5000C000)
215 #define IMX_CSPI2_BASE		(0x50010000)
216 #define IMX_SSI2_BASE		(0x50014000)
217 #define IMX_ESAI_BASE		(0x50018000)
218 #define IMX_ATA_DMA_BASE	(0x50020000)
219 #define IMX_SIM1_BASE		(0x50024000)
220 #define IMX_SIM2_BASE		(0x50028000)
221 #define IMX_UART5_BASE		(0x5002C000)
222 #define IMX_TSC_BASE		(0x50030000)
223 #define IMX_SSI1_BASE		(0x50034000)
224 #define IMX_FEC_BASE		(0x50038000)
225 #define IMX_SPBA_CTRL_BASE	(0x5003C000)
226 
227 /* AIPS 2 */
228 #define IMX_AIPS2_BASE		(0x53F00000)
229 #define IMX_CCM_BASE		(0x53F80000)
230 #define IMX_GPT4_BASE		(0x53F84000)
231 #define IMX_GPT3_BASE		(0x53F88000)
232 #define IMX_GPT2_BASE		(0x53F8C000)
233 #define IMX_GPT1_BASE		(0x53F90000)
234 #define IMX_EPIT1_BASE		(0x53F94000)
235 #define IMX_EPIT2_BASE		(0x53F98000)
236 #define IMX_GPIO4_BASE		(0x53F9C000)
237 #define IMX_PWM2_BASE		(0x53FA0000)
238 #define IMX_GPIO3_BASE		(0x53FA4000)
239 #define IMX_PWM3_BASE		(0x53FA8000)
240 #define IMX_SCC_BASE		(0x53FAC000)
241 #define IMX_SCM_BASE		(0x53FAE000)
242 #define IMX_SMN_BASE		(0x53FAF000)
243 #define IMX_RNGD_BASE		(0x53FB0000)
244 #define IMX_MMC_SDHC1_BASE	(0x53FB4000)
245 #define IMX_MMC_SDHC2_BASE	(0x53FB8000)
246 #define IMX_LCDC_BASE		(0x53FBC000)
247 #define IMX_SLCDC_BASE		(0x53FC0000)
248 #define IMX_PWM4_BASE		(0x53FC8000)
249 #define IMX_GPIO1_BASE		(0x53FCC000)
250 #define IMX_GPIO2_BASE		(0x53FD0000)
251 #define IMX_SDMA_BASE		(0x53FD4000)
252 #define IMX_WDT_BASE		(0x53FDC000)
253 #define IMX_PWM1_BASE		(0x53FE0000)
254 #define IMX_RTIC_BASE		(0x53FEC000)
255 #define IMX_IIM_BASE		(0x53FF0000)
256 #define IMX_USB_BASE		(0x53FF4000)
257 #define IMX_CSI_BASE		(0x53FF8000)
258 #define IMX_DRYICE_BASE		(0x53FFC000)
259 
260 #define IMX_ARM926_ROMPATCH	(0x60000000)
261 #define IMX_ARM926_ASIC		(0x68000000)
262 
263 /* 128K Internal Static RAM */
264 #define IMX_RAM_BASE		(0x78000000)
265 
266 /* SDRAM BANKS */
267 #define IMX_SDRAM_BANK0_BASE	(0x80000000)
268 #define IMX_SDRAM_BANK1_BASE	(0x90000000)
269 
270 #define IMX_WEIM_CS0		(0xA0000000)
271 #define IMX_WEIM_CS1		(0xA8000000)
272 #define IMX_WEIM_CS2		(0xB0000000)
273 #define IMX_WEIM_CS3		(0xB2000000)
274 #define IMX_WEIM_CS4		(0xB4000000)
275 #define IMX_ESDRAMC_BASE	(0xB8001000)
276 #define IMX_WEIM_CTRL_BASE	(0xB8002000)
277 #define IMX_M3IF_CTRL_BASE	(0xB8003000)
278 #define IMX_EMI_CTRL_BASE	(0xB8004000)
279 
280 /* NAND Flash Controller */
281 #define IMX_NFC_BASE		(0xBB000000)
282 #define NFC_BASE_ADDR		IMX_NFC_BASE
283 
284 /* CCM bitfields */
285 #define CCM_PLL_MFI_SHIFT	10
286 #define CCM_PLL_MFI_MASK	0xf
287 #define CCM_PLL_MFN_SHIFT	0
288 #define CCM_PLL_MFN_MASK	0x3ff
289 #define CCM_PLL_MFD_SHIFT	16
290 #define CCM_PLL_MFD_MASK	0x3ff
291 #define CCM_PLL_PD_SHIFT	26
292 #define CCM_PLL_PD_MASK		0xf
293 #define CCM_CCTL_ARM_DIV_SHIFT	30
294 #define CCM_CCTL_ARM_DIV_MASK	3
295 #define CCM_CCTL_AHB_DIV_SHIFT	28
296 #define CCM_CCTL_AHB_DIV_MASK	3
297 #define CCM_CCTL_ARM_SRC	(1 << 14)
298 #define CCM_CGR1_GPT1		(1 << 19)
299 #define CCM_PERCLK_REG(clk)	(clk / 4)
300 #define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
301 #define CCM_PERCLK_MASK		0x3f
302 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
303 #define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
304 
305 /* ESDRAM Controller register bitfields */
306 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
307 #define ESDCTL_BL		(1 << 7)
308 #define ESDCTL_FP		(1 << 8)
309 #define ESDCTL_PWDT(x)		(((x) & 3) << 10)
310 #define ESDCTL_SREFR(x)		(((x) & 7) << 13)
311 #define ESDCTL_DSIZ_16_UPPER	(0 << 16)
312 #define ESDCTL_DSIZ_16_LOWER	(1 << 16)
313 #define ESDCTL_DSIZ_32		(2 << 16)
314 #define ESDCTL_COL8		(0 << 20)
315 #define ESDCTL_COL9		(1 << 20)
316 #define ESDCTL_COL10		(2 << 20)
317 #define ESDCTL_ROW11		(0 << 24)
318 #define ESDCTL_ROW12		(1 << 24)
319 #define ESDCTL_ROW13		(2 << 24)
320 #define ESDCTL_ROW14		(3 << 24)
321 #define ESDCTL_ROW15		(4 << 24)
322 #define ESDCTL_SP		(1 << 27)
323 #define ESDCTL_SMODE_NORMAL	(0 << 28)
324 #define ESDCTL_SMODE_PRECHARGE	(1 << 28)
325 #define ESDCTL_SMODE_AUTO_REF	(2 << 28)
326 #define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
327 #define ESDCTL_SMODE_MAN_REF	(4 << 28)
328 #define ESDCTL_SDE		(1 << 31)
329 
330 #define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
331 #define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
332 #define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
333 #define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
334 #define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
335 #define ESDCFG_TWR		(1 << 15)
336 #define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
337 #define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
338 #define ESDCFG_TWTR		(1 << 20)
339 #define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
340 
341 #define ESDMISC_RST		(1 << 1)
342 #define ESDMISC_MDDREN		(1 << 2)
343 #define ESDMISC_MDDR_DL_RST	(1 << 3)
344 #define ESDMISC_MDDR_MDIS	(1 << 4)
345 #define ESDMISC_LHD		(1 << 5)
346 #define ESDMISC_MA10_SHARE	(1 << 6)
347 #define ESDMISC_SDRAM_RDY	(1 << 31)
348 
349 /* GPT bits */
350 #define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
351 #define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
352 #define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
353 #define GPT_CTRL_TEN		1		/* Timer enable	*/
354 
355 /* WDOG enable */
356 #define WCR_WDE 		0x04
357 #define WSR_UNLOCK1		0x5555
358 #define WSR_UNLOCK2		0xAAAA
359 
360 /* Names used in GPIO driver */
361 #define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
362 #define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
363 #define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
364 #define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
365 
366 #endif				/* _IMX_REGS_H */
367