1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * Derived from drivers/spi/mpc8xxx_spi.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __KW_SPI_H__ 12 #define __KW_SPI_H__ 13 14 /* SPI Registers on kirkwood SOC */ 15 struct kwspi_registers { 16 u32 ctrl; /* 0x10600 */ 17 u32 cfg; /* 0x10604 */ 18 u32 dout; /* 0x10608 */ 19 u32 din; /* 0x1060c */ 20 u32 irq_cause; /* 0x10610 */ 21 u32 irq_mask; /* 0x10614 */ 22 }; 23 24 /* They are used to define CONFIG_SYS_KW_SPI_MPP 25 * each of the below #defines selects which mpp is 26 * configured for each SPI signal in spi_claim_bus 27 * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) 28 * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) 29 * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) 30 */ 31 #define MOSI_MPP6 (1 << 0) 32 #define SCK_MPP10 (1 << 1) 33 #define MISO_MPP11 (1 << 2) 34 35 #define KWSPI_CLKPRESCL_MASK 0x1f 36 #define KWSPI_CLKPRESCL_MIN 0x12 37 #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ 38 #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ 39 #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ 40 #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ 41 #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ 42 #define KWSPI_XFERLEN_1BYTE 0 43 #define KWSPI_XFERLEN_2BYTE (1 << 5) 44 #define KWSPI_XFERLEN_MASK (1 << 5) 45 #define KWSPI_ADRLEN_1BYTE 0 46 #define KWSPI_ADRLEN_2BYTE (1 << 8) 47 #define KWSPI_ADRLEN_3BYTE (2 << 8) 48 #define KWSPI_ADRLEN_4BYTE (3 << 8) 49 #define KWSPI_ADRLEN_MASK (3 << 8) 50 #define KWSPI_TIMEOUT 10000 51 52 #endif /* __KW_SPI_H__ */ 53