1 /* 2 * (C) Copyright 2016 Carlo Caione <carlo@caione.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __SD_EMMC_H__ 8 #define __SD_EMMC_H__ 9 10 #include <mmc.h> 11 12 #define SDIO_PORT_A 0 13 #define SDIO_PORT_B 1 14 #define SDIO_PORT_C 2 15 16 #define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ 17 #define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ 18 19 #define MESON_SD_EMMC_CLOCK 0x00 20 #define CLK_MAX_DIV 63 21 #define CLK_SRC_24M (0 << 6) 22 #define CLK_SRC_DIV2 (1 << 6) 23 #define CLK_CO_PHASE_000 (0 << 8) 24 #define CLK_CO_PHASE_090 (1 << 8) 25 #define CLK_CO_PHASE_180 (2 << 8) 26 #define CLK_CO_PHASE_270 (3 << 8) 27 #define CLK_TX_PHASE_000 (0 << 10) 28 #define CLK_TX_PHASE_090 (1 << 10) 29 #define CLK_TX_PHASE_180 (2 << 10) 30 #define CLK_TX_PHASE_270 (3 << 10) 31 #define CLK_ALWAYS_ON BIT(24) 32 33 #define MESON_SD_EMMC_CFG 0x44 34 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 35 #define CFG_BUS_WIDTH_1 0 36 #define CFG_BUS_WIDTH_4 1 37 #define CFG_BUS_WIDTH_8 2 38 #define CFG_BL_LEN_MASK GENMASK(7, 4) 39 #define CFG_BL_LEN_SHIFT 4 40 #define CFG_BL_LEN_512 (9 << 4) 41 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 42 #define CFG_RESP_TIMEOUT_256 (8 << 8) 43 #define CFG_RC_CC_MASK GENMASK(15, 12) 44 #define CFG_RC_CC_16 (4 << 12) 45 #define CFG_SDCLK_ALWAYS_ON BIT(18) 46 #define CFG_AUTO_CLK BIT(23) 47 48 #define MESON_SD_EMMC_STATUS 0x48 49 #define STATUS_MASK GENMASK(15, 0) 50 #define STATUS_ERR_MASK GENMASK(12, 0) 51 #define STATUS_RXD_ERR_MASK GENMASK(7, 0) 52 #define STATUS_TXD_ERR BIT(8) 53 #define STATUS_DESC_ERR BIT(9) 54 #define STATUS_RESP_ERR BIT(10) 55 #define STATUS_RESP_TIMEOUT BIT(11) 56 #define STATUS_DESC_TIMEOUT BIT(12) 57 #define STATUS_END_OF_CHAIN BIT(13) 58 59 #define MESON_SD_EMMC_IRQ_EN 0x4c 60 61 #define MESON_SD_EMMC_CMD_CFG 0x50 62 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 63 #define CMD_CFG_BLOCK_MODE BIT(9) 64 #define CMD_CFG_R1B BIT(10) 65 #define CMD_CFG_END_OF_CHAIN BIT(11) 66 #define CMD_CFG_TIMEOUT_4S (12 << 12) 67 #define CMD_CFG_NO_RESP BIT(16) 68 #define CMD_CFG_DATA_IO BIT(18) 69 #define CMD_CFG_DATA_WR BIT(19) 70 #define CMD_CFG_RESP_NOCRC BIT(20) 71 #define CMD_CFG_RESP_128 BIT(21) 72 #define CMD_CFG_CMD_INDEX_SHIFT 24 73 #define CMD_CFG_OWNER BIT(31) 74 75 #define MESON_SD_EMMC_CMD_ARG 0x54 76 #define MESON_SD_EMMC_CMD_DAT 0x58 77 #define MESON_SD_EMMC_CMD_RSP 0x5c 78 #define MESON_SD_EMMC_CMD_RSP1 0x60 79 #define MESON_SD_EMMC_CMD_RSP2 0x64 80 #define MESON_SD_EMMC_CMD_RSP3 0x68 81 82 struct meson_mmc_platdata { 83 struct mmc_config cfg; 84 struct mmc mmc; 85 void *regbase; 86 void *w_buf; 87 }; 88 89 #endif 90