1*f0f3762cSNeil Armstrong /* SPDX-License-Identifier: GPL-2.0+ */ 2*f0f3762cSNeil Armstrong /* 3*f0f3762cSNeil Armstrong * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 4*f0f3762cSNeil Armstrong */ 5*f0f3762cSNeil Armstrong 6*f0f3762cSNeil Armstrong #ifndef __GX_H__ 7*f0f3762cSNeil Armstrong #define __GX_H__ 8*f0f3762cSNeil Armstrong 9*f0f3762cSNeil Armstrong #define GX_FIRMWARE_MEM_SIZE 0x1000000 10*f0f3762cSNeil Armstrong 11*f0f3762cSNeil Armstrong #define GX_AOBUS_BASE 0xc8100000 12*f0f3762cSNeil Armstrong #define GX_PERIPHS_BASE 0xc8834400 13*f0f3762cSNeil Armstrong #define GX_HIU_BASE 0xc883c000 14*f0f3762cSNeil Armstrong #define GX_ETH_BASE 0xc9410000 15*f0f3762cSNeil Armstrong 16*f0f3762cSNeil Armstrong /* Always-On Peripherals registers */ 17*f0f3762cSNeil Armstrong #define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) 18*f0f3762cSNeil Armstrong 19*f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) 20*f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) 21*f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) 22*f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) 23*f0f3762cSNeil Armstrong 24*f0f3762cSNeil Armstrong #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 25*f0f3762cSNeil Armstrong #define GX_AO_MEM_SIZE_SHIFT 16 26*f0f3762cSNeil Armstrong #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 27*f0f3762cSNeil Armstrong #define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 28*f0f3762cSNeil Armstrong #define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF 29*f0f3762cSNeil Armstrong 30*f0f3762cSNeil Armstrong /* Peripherals registers */ 31*f0f3762cSNeil Armstrong #define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) 32*f0f3762cSNeil Armstrong 33*f0f3762cSNeil Armstrong /* GPIO registers 0 to 6 */ 34*f0f3762cSNeil Armstrong #define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) 35*f0f3762cSNeil Armstrong #define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) 36*f0f3762cSNeil Armstrong #define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) 37*f0f3762cSNeil Armstrong #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) 38*f0f3762cSNeil Armstrong 39*f0f3762cSNeil Armstrong #define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) 40*f0f3762cSNeil Armstrong #define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) 41*f0f3762cSNeil Armstrong #define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) 42*f0f3762cSNeil Armstrong #define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) 43*f0f3762cSNeil Armstrong 44*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_PHY_INTF BIT(0) 45*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 46*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 47*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_PHY_CLK_EN BIT(10) 48*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) 49*f0f3762cSNeil Armstrong #define GX_ETH_REG_0_CLK_EN BIT(12) 50*f0f3762cSNeil Armstrong 51*f0f3762cSNeil Armstrong /* HIU registers */ 52*f0f3762cSNeil Armstrong #define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) 53*f0f3762cSNeil Armstrong 54*f0f3762cSNeil Armstrong #define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) 55*f0f3762cSNeil Armstrong 56*f0f3762cSNeil Armstrong /* Ethernet memory power domain */ 57*f0f3762cSNeil Armstrong #define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 58*f0f3762cSNeil Armstrong 59*f0f3762cSNeil Armstrong /* Clock gates */ 60*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50) 61*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51) 62*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52) 63*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53) 64*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54) 65*f0f3762cSNeil Armstrong 66*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_0_I2C BIT(9) 67*f0f3762cSNeil Armstrong #define GX_GCLK_MPEG_1_ETH BIT(3) 68*f0f3762cSNeil Armstrong 69*f0f3762cSNeil Armstrong #endif /* __GX_H__ */ 70