1f0f3762cSNeil Armstrong /* SPDX-License-Identifier: GPL-2.0+ */ 2f0f3762cSNeil Armstrong /* 3f0f3762cSNeil Armstrong * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 4f0f3762cSNeil Armstrong */ 5f0f3762cSNeil Armstrong 6f0f3762cSNeil Armstrong #ifndef __GX_H__ 7f0f3762cSNeil Armstrong #define __GX_H__ 8f0f3762cSNeil Armstrong 9f0f3762cSNeil Armstrong #define GX_FIRMWARE_MEM_SIZE 0x1000000 10f0f3762cSNeil Armstrong 11f0f3762cSNeil Armstrong #define GX_AOBUS_BASE 0xc8100000 12f0f3762cSNeil Armstrong #define GX_PERIPHS_BASE 0xc8834400 13f0f3762cSNeil Armstrong #define GX_HIU_BASE 0xc883c000 14f0f3762cSNeil Armstrong #define GX_ETH_BASE 0xc9410000 15f0f3762cSNeil Armstrong 16f0f3762cSNeil Armstrong /* Always-On Peripherals registers */ 17f0f3762cSNeil Armstrong #define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2)) 18f0f3762cSNeil Armstrong 19f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90) 20f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93) 21f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94) 22f0f3762cSNeil Armstrong #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95) 23f0f3762cSNeil Armstrong 24*d96a782dSNeil Armstrong #define GX_AO_BOOT_DEVICE 0xF 25f0f3762cSNeil Armstrong #define GX_AO_MEM_SIZE_MASK 0xFFFF0000 26f0f3762cSNeil Armstrong #define GX_AO_MEM_SIZE_SHIFT 16 27f0f3762cSNeil Armstrong #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 28f0f3762cSNeil Armstrong #define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16 29f0f3762cSNeil Armstrong #define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF 30f0f3762cSNeil Armstrong 31f0f3762cSNeil Armstrong /* Peripherals registers */ 32f0f3762cSNeil Armstrong #define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2)) 33f0f3762cSNeil Armstrong 34f0f3762cSNeil Armstrong /* GPIO registers 0 to 6 */ 35f0f3762cSNeil Armstrong #define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) 36f0f3762cSNeil Armstrong #define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0) 37f0f3762cSNeil Armstrong #define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1) 38f0f3762cSNeil Armstrong #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2) 39f0f3762cSNeil Armstrong 40f0f3762cSNeil Armstrong #define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50) 41f0f3762cSNeil Armstrong #define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51) 42f0f3762cSNeil Armstrong #define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56) 43f0f3762cSNeil Armstrong #define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57) 44f0f3762cSNeil Armstrong 45f0f3762cSNeil Armstrong #define GX_ETH_REG_0_PHY_INTF BIT(0) 46f0f3762cSNeil Armstrong #define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 47f0f3762cSNeil Armstrong #define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 48f0f3762cSNeil Armstrong #define GX_ETH_REG_0_PHY_CLK_EN BIT(10) 49f0f3762cSNeil Armstrong #define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11) 50f0f3762cSNeil Armstrong #define GX_ETH_REG_0_CLK_EN BIT(12) 51f0f3762cSNeil Armstrong 52f0f3762cSNeil Armstrong /* HIU registers */ 53f0f3762cSNeil Armstrong #define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2)) 54f0f3762cSNeil Armstrong 55f0f3762cSNeil Armstrong #define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40) 56f0f3762cSNeil Armstrong 57f0f3762cSNeil Armstrong /* Ethernet memory power domain */ 58f0f3762cSNeil Armstrong #define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 59f0f3762cSNeil Armstrong 60f0f3762cSNeil Armstrong #endif /* __GX_H__ */ 61