1485bba39SNeil Armstrong /* SPDX-License-Identifier: GPL-2.0+ */
2485bba39SNeil Armstrong /*
3485bba39SNeil Armstrong  * Copyright (C) 2018 BayLibre, SAS
4485bba39SNeil Armstrong  * Author: Neil Armstrong <narmstrong@baylibre.com>
5485bba39SNeil Armstrong  */
6485bba39SNeil Armstrong 
7485bba39SNeil Armstrong #ifndef __AXG_H__
8485bba39SNeil Armstrong #define __AXG_H__
9485bba39SNeil Armstrong 
10485bba39SNeil Armstrong #define AXG_AOBUS_BASE		0xff800000
11485bba39SNeil Armstrong #define AXG_PERIPHS_BASE	0xff634400
12485bba39SNeil Armstrong #define AXG_HIU_BASE		0xff63c000
13485bba39SNeil Armstrong #define AXG_ETH_BASE		0xff3f0000
14485bba39SNeil Armstrong 
15485bba39SNeil Armstrong /* Always-On Peripherals registers */
16485bba39SNeil Armstrong #define AXG_AO_ADDR(off)	(AXG_AOBUS_BASE + ((off) << 2))
17485bba39SNeil Armstrong 
18485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG0	AXG_AO_ADDR(0x90)
19485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG3	AXG_AO_ADDR(0x93)
20485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
21485bba39SNeil Armstrong #define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
22485bba39SNeil Armstrong 
23*d96a782dSNeil Armstrong #define AXG_AO_BOOT_DEVICE	0xF
24485bba39SNeil Armstrong #define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
25485bba39SNeil Armstrong #define AXG_AO_MEM_SIZE_SHIFT	16
26485bba39SNeil Armstrong #define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
27485bba39SNeil Armstrong #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT	16
28485bba39SNeil Armstrong #define AXG_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
29485bba39SNeil Armstrong 
30485bba39SNeil Armstrong /* Peripherals registers */
31485bba39SNeil Armstrong #define AXG_PERIPHS_ADDR(off)	(AXG_PERIPHS_BASE + ((off) << 2))
32485bba39SNeil Armstrong 
33485bba39SNeil Armstrong #define AXG_ETH_REG_0		AXG_PERIPHS_ADDR(0x50)
34485bba39SNeil Armstrong #define AXG_ETH_REG_1		AXG_PERIPHS_ADDR(0x51)
35485bba39SNeil Armstrong 
36485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
37485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_INTF_RMII	BIT(2)
38485bba39SNeil Armstrong #define AXG_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
39485bba39SNeil Armstrong #define AXG_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
40485bba39SNeil Armstrong #define AXG_ETH_REG_0_PHY_CLK_EN	BIT(10)
41485bba39SNeil Armstrong #define AXG_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
42485bba39SNeil Armstrong #define AXG_ETH_REG_0_CLK_EN		BIT(12)
43485bba39SNeil Armstrong 
44485bba39SNeil Armstrong /* HIU registers */
45485bba39SNeil Armstrong #define AXG_HIU_ADDR(off)	(AXG_HIU_BASE + ((off) << 2))
46485bba39SNeil Armstrong 
47485bba39SNeil Armstrong #define AXG_MEM_PD_REG_0	AXG_HIU_ADDR(0x40)
48485bba39SNeil Armstrong 
49485bba39SNeil Armstrong /* Ethernet memory power domain */
50485bba39SNeil Armstrong #define AXG_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
51485bba39SNeil Armstrong 
52485bba39SNeil Armstrong #endif /* __AXG_H__ */
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