1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_NS_ACCESS_H_ 8 #define __FSL_NS_ACCESS_H_ 9 10 enum csu_cslx_ind { 11 CSU_CSLX_PCIE2_IO = 0, 12 CSU_CSLX_PCIE1_IO, 13 CSU_CSLX_MG2TPR_IP, 14 CSU_CSLX_IFC_MEM, 15 CSU_CSLX_OCRAM, 16 CSU_CSLX_GIC, 17 CSU_CSLX_PCIE1, 18 CSU_CSLX_OCRAM2, 19 CSU_CSLX_QSPI_MEM, 20 CSU_CSLX_PCIE2, 21 CSU_CSLX_SATA, 22 CSU_CSLX_USB3, 23 CSU_CSLX_SERDES = 32, 24 CSU_CSLX_QDMA, 25 CSU_CSLX_LPUART2, 26 CSU_CSLX_LPUART1, 27 CSU_CSLX_LPUART4, 28 CSU_CSLX_LPUART3, 29 CSU_CSLX_LPUART6, 30 CSU_CSLX_LPUART5, 31 CSU_CSLX_DSPI2 = 40, 32 CSU_CSLX_DSPI1, 33 CSU_CSLX_QSPI, 34 CSU_CSLX_ESDHC, 35 CSU_CSLX_2D_ACE, 36 CSU_CSLX_IFC, 37 CSU_CSLX_I2C1, 38 CSU_CSLX_USB2, 39 CSU_CSLX_I2C3, 40 CSU_CSLX_I2C2, 41 CSU_CSLX_DUART2 = 50, 42 CSU_CSLX_DUART1, 43 CSU_CSLX_WDT2, 44 CSU_CSLX_WDT1, 45 CSU_CSLX_EDMA, 46 CSU_CSLX_SYS_CNT, 47 CSU_CSLX_DMA_MUX2, 48 CSU_CSLX_DMA_MUX1, 49 CSU_CSLX_DDR, 50 CSU_CSLX_QUICC, 51 CSU_CSLX_DCFG_CCU_RCPM = 60, 52 CSU_CSLX_SECURE_BOOTROM, 53 CSU_CSLX_SFP, 54 CSU_CSLX_TMU, 55 CSU_CSLX_SECURE_MONITOR, 56 CSU_CSLX_RESERVED0, 57 CSU_CSLX_ETSEC1, 58 CSU_CSLX_SEC5_5, 59 CSU_CSLX_ETSEC3, 60 CSU_CSLX_ETSEC2, 61 CSU_CSLX_GPIO2 = 70, 62 CSU_CSLX_GPIO1, 63 CSU_CSLX_GPIO4, 64 CSU_CSLX_GPIO3, 65 CSU_CSLX_PLATFORM_CONT, 66 CSU_CSLX_CSU, 67 CSU_CSLX_ASRC, 68 CSU_CSLX_SPDIF, 69 CSU_CSLX_FLEXCAN2, 70 CSU_CSLX_FLEXCAN1, 71 CSU_CSLX_FLEXCAN4 = 80, 72 CSU_CSLX_FLEXCAN3, 73 CSU_CSLX_SAI2, 74 CSU_CSLX_SAI1, 75 CSU_CSLX_SAI4, 76 CSU_CSLX_SAI3, 77 CSU_CSLX_FTM2, 78 CSU_CSLX_FTM1, 79 CSU_CSLX_FTM4, 80 CSU_CSLX_FTM3, 81 CSU_CSLX_FTM6 = 90, 82 CSU_CSLX_FTM5, 83 CSU_CSLX_FTM8, 84 CSU_CSLX_FTM7, 85 CSU_CSLX_EPU, 86 CSU_CSLX_COP_DCSR, 87 CSU_CSLX_DDI, 88 CSU_CSLX_GDI, 89 CSU_CSLX_RESERVED1, 90 CSU_CSLX_USB3_PHY = 116, 91 CSU_CSLX_RESERVED2, 92 CSU_CSLX_MAX, 93 }; 94 95 static struct csu_ns_dev ns_dev[] = { 96 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 97 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 98 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 99 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 100 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 101 { CSU_CSLX_GIC, CSU_ALL_RW }, 102 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 103 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 104 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 105 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 106 { CSU_CSLX_SATA, CSU_ALL_RW }, 107 { CSU_CSLX_USB3, CSU_ALL_RW }, 108 { CSU_CSLX_SERDES, CSU_ALL_RW }, 109 { CSU_CSLX_QDMA, CSU_ALL_RW }, 110 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 111 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 112 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 113 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 114 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 115 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 116 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 117 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 118 { CSU_CSLX_QSPI, CSU_ALL_RW }, 119 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 120 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 121 { CSU_CSLX_IFC, CSU_ALL_RW }, 122 { CSU_CSLX_I2C1, CSU_ALL_RW }, 123 { CSU_CSLX_USB2, CSU_ALL_RW }, 124 { CSU_CSLX_I2C3, CSU_ALL_RW }, 125 { CSU_CSLX_I2C2, CSU_ALL_RW }, 126 { CSU_CSLX_DUART2, CSU_ALL_RW }, 127 { CSU_CSLX_DUART1, CSU_ALL_RW }, 128 { CSU_CSLX_WDT2, CSU_ALL_RW }, 129 { CSU_CSLX_WDT1, CSU_ALL_RW }, 130 { CSU_CSLX_EDMA, CSU_ALL_RW }, 131 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 132 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 133 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 134 { CSU_CSLX_DDR, CSU_ALL_RW }, 135 { CSU_CSLX_QUICC, CSU_ALL_RW }, 136 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 137 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 138 { CSU_CSLX_SFP, CSU_ALL_RW }, 139 { CSU_CSLX_TMU, CSU_ALL_RW }, 140 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 141 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 142 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 143 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 144 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 145 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 146 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 147 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 148 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 149 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 150 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 151 { CSU_CSLX_CSU, CSU_ALL_RW }, 152 { CSU_CSLX_ASRC, CSU_ALL_RW }, 153 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 154 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 155 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 156 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 157 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 158 { CSU_CSLX_SAI2, CSU_ALL_RW }, 159 { CSU_CSLX_SAI1, CSU_ALL_RW }, 160 { CSU_CSLX_SAI4, CSU_ALL_RW }, 161 { CSU_CSLX_SAI3, CSU_ALL_RW }, 162 { CSU_CSLX_FTM2, CSU_ALL_RW }, 163 { CSU_CSLX_FTM1, CSU_ALL_RW }, 164 { CSU_CSLX_FTM4, CSU_ALL_RW }, 165 { CSU_CSLX_FTM3, CSU_ALL_RW }, 166 { CSU_CSLX_FTM6, CSU_ALL_RW }, 167 { CSU_CSLX_FTM5, CSU_ALL_RW }, 168 { CSU_CSLX_FTM8, CSU_ALL_RW }, 169 { CSU_CSLX_FTM7, CSU_ALL_RW }, 170 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 171 { CSU_CSLX_EPU, CSU_ALL_RW }, 172 { CSU_CSLX_GDI, CSU_ALL_RW }, 173 { CSU_CSLX_DDI, CSU_ALL_RW }, 174 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 175 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 176 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 177 }; 178 179 #endif 180