1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_LS102XA_DEVDIS_H_ 7 #define __FSL_LS102XA_DEVDIS_H_ 8 9 #include <fsl_devdis.h> 10 11 const struct devdis_table devdis_tbl[] = { 12 { "pbl", 0x0, 0x80000000 }, /* PBL */ 13 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ 14 { "qdma", 0x0, 0x800000 }, /* qDMA */ 15 { "edma", 0x0, 0x400000 }, /* eDMA */ 16 { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ 17 { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ 18 { "sata", 0x0, 0x8000 }, /* SATA */ 19 { "sec", 0x0, 0x200 }, /* SEC */ 20 { "dcu", 0x0, 0x2 }, /* Display controller Unit */ 21 { "qe", 0x0, 0x1 }, /* QUICC Engine */ 22 { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ 23 { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ 24 { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ 25 { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ 26 { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ 27 { "duart1", 0x3, 0x20000000 }, /* DUART1 */ 28 { "duart2", 0x3, 0x10000000 }, /* DUART2 */ 29 { "qspi", 0x3, 0x8000000 }, /* QSPI */ 30 { "ddr", 0x4, 0x80000000 }, /* DDR */ 31 { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ 32 { "ifc", 0x4, 0x800000 }, /* IFC */ 33 { "gpio", 0x4, 0x400000 }, /* GPIO */ 34 { "dbg", 0x4, 0x200000 }, /* DBG */ 35 { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ 36 { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ 37 { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ 38 { "secmon", 0x4, 0x4000 }, /* Security Monitor */ 39 { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ 40 { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ 41 { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ 42 { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ 43 { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ 44 { "asrc", 0x4, 0x20 }, /* ASRC */ 45 { "spdif", 0x4, 0x10 }, /* SPDIF */ 46 { "i2c1", 0x4, 0x4 }, /* I2C1 */ 47 { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ 48 { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ 49 }; 50 51 #endif 52