1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 #define __ASM_ARCH_LS102XA_IMMAP_H_
9 
10 #define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
11 #define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
12 #define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
14 #define IS_SVR_REV(svr, maj, min) \
15 		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
16 
17 #define SOC_VER_SLS1020		0x00
18 #define SOC_VER_LS1020		0x10
19 #define SOC_VER_LS1021		0x11
20 #define SOC_VER_LS1022		0x12
21 
22 #define SOC_MAJOR_VER_1_0	0x1
23 #define SOC_MAJOR_VER_2_0	0x2
24 
25 #define CCSR_BRR_OFFSET		0xe4
26 #define CCSR_SCRATCHRW1_OFFSET	0x200
27 
28 #define RCWSR0_SYS_PLL_RAT_SHIFT	25
29 #define RCWSR0_SYS_PLL_RAT_MASK		0x1f
30 #define RCWSR0_MEM_PLL_RAT_SHIFT	16
31 #define RCWSR0_MEM_PLL_RAT_MASK		0x3f
32 
33 #define RCWSR4_SRDS1_PRTCL_SHIFT	24
34 #define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
35 
36 #define TIMER_COMP_VAL			0xffffffffffffffffull
37 #define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
38 #define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
39 
40 #define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
41 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
42 
43 #define DCFG_DCSR_PORCR1		0
44 
45 /*
46  * Define default values for some CCSR macros to make header files cleaner
47  *
48  * To completely disable CCSR relocation in a board header file, define
49  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
50  * to a value that is the same as CONFIG_SYS_CCSRBAR.
51  */
52 
53 #ifdef CONFIG_SYS_CCSRBAR_PHYS
54 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
55 #endif
56 
57 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
58 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
59 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
60 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
61 #endif
62 
63 #ifndef CONFIG_SYS_CCSRBAR
64 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
65 #endif
66 
67 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
68 #ifdef CONFIG_PHYS_64BIT
69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
70 #else
71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
72 #endif
73 #endif
74 
75 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
77 #endif
78 
79 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
80 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
81 
82 struct sys_info {
83 	unsigned long freq_processor[CONFIG_MAX_CPUS];
84 	unsigned long freq_systembus;
85 	unsigned long freq_ddrbus;
86 	unsigned long freq_localbus;
87 };
88 
89 /* Device Configuration and Pin Control */
90 struct ccsr_gur {
91 	u32     porsr1;         /* POR status 1 */
92 	u32     porsr2;         /* POR status 2 */
93 	u8      res_008[0x20-0x8];
94 	u32     gpporcr1;       /* General-purpose POR configuration */
95 	u32	gpporcr2;
96 	u32     dcfg_fusesr;    /* Fuse status register */
97 	u8      res_02c[0x70-0x2c];
98 	u32     devdisr;        /* Device disable control */
99 	u32     devdisr2;       /* Device disable control 2 */
100 	u32     devdisr3;       /* Device disable control 3 */
101 	u32     devdisr4;       /* Device disable control 4 */
102 	u32     devdisr5;       /* Device disable control 5 */
103 	u8      res_084[0x94-0x84];
104 	u32     coredisru;      /* uppper portion for support of 64 cores */
105 	u32     coredisrl;      /* lower portion for support of 64 cores */
106 	u8      res_09c[0xa4-0x9c];
107 	u32     svr;            /* System version */
108 	u8	res_0a8[0xb0-0xa8];
109 	u32	rstcr;		/* Reset control */
110 	u32	rstrqpblsr;	/* Reset request preboot loader status */
111 	u8	res_0b8[0xc0-0xb8];
112 	u32	rstrqmr1;	/* Reset request mask */
113 	u8	res_0c4[0xc8-0xc4];
114 	u32	rstrqsr1;	/* Reset request status */
115 	u8	res_0cc[0xd4-0xcc];
116 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
117 	u8	res_0d8[0xdc-0xd8];
118 	u32	rstrqwdtsrl;	/* Reset request WDT status */
119 	u8	res_0e0[0xe4-0xe0];
120 	u32	brrl;		/* Boot release */
121 	u8      res_0e8[0x100-0xe8];
122 	u32     rcwsr[16];      /* Reset control word status */
123 #define RCW_SB_EN_REG_INDEX	7
124 #define RCW_SB_EN_MASK		0x00200000
125 	u8      res_140[0x200-0x140];
126 	u32     scratchrw[4];  /* Scratch Read/Write */
127 	u8      res_210[0x300-0x210];
128 	u32     scratchw1r[4];  /* Scratch Read (Write once) */
129 	u8      res_310[0x400-0x310];
130 	u32	crstsr;
131 	u8      res_404[0x550-0x404];
132 	u32	sataliodnr;
133 	u8	res_554[0x604-0x554];
134 	u32	pamubypenr;
135 	u32	dmacr1;
136 	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
137 	u32     tp_ityp[64];    /* Topology Initiator Type Register */
138 	struct {
139 		u32     upper;
140 		u32     lower;
141 	} tp_cluster[1];        /* Core Cluster n Topology Register */
142 	u8	res_848[0xe60-0x848];
143 	u32	ddrclkdr;
144 	u8	res_e60[0xe68-0xe64];
145 	u32	ifcclkdr;
146 	u8	res_e68[0xe80-0xe6c];
147 	u32	sdhcpcr;
148 };
149 
150 #define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
151 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
152 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
153 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
154 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
155 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
156 #define SCFG_QSPI_CLKSEL		0xc0100000
157 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
158 #define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
159 #define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
160 #define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
161 #define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
162 #define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
163 #define SCFG_ENDIANCR_LE		0x80000000
164 
165 /* Supplemental Configuration Unit */
166 struct ccsr_scfg {
167 	u32 dpslpcr;
168 	u32 resv0[2];
169 	u32 etsecclkdpslpcr;
170 	u32 resv1[5];
171 	u32 fuseovrdcr;
172 	u32 pixclkcr;
173 	u32 resv2[5];
174 	u32 spimsicr;
175 	u32 resv3[6];
176 	u32 pex1pmwrcr;
177 	u32 pex1pmrdsr;
178 	u32 resv4[3];
179 	u32 usb3prm1cr;
180 	u32 usb4prm2cr;
181 	u32 pex1rdmsgpldlsbsr;
182 	u32 pex1rdmsgpldmsbsr;
183 	u32 pex2rdmsgpldlsbsr;
184 	u32 pex2rdmsgpldmsbsr;
185 	u32 pex1rdmmsgrqsr;
186 	u32 pex2rdmmsgrqsr;
187 	u32 spimsiclrcr;
188 	u32 pexmscportsr[2];
189 	u32 pex2pmwrcr;
190 	u32 resv5[24];
191 	u32 mac1_streamid;
192 	u32 mac2_streamid;
193 	u32 mac3_streamid;
194 	u32 pex1_streamid;
195 	u32 pex2_streamid;
196 	u32 dma_streamid;
197 	u32 sata_streamid;
198 	u32 usb3_streamid;
199 	u32 qe_streamid;
200 	u32 sdhc_streamid;
201 	u32 adma_streamid;
202 	u32 letechsftrstcr;
203 	u32 core0_sft_rst;
204 	u32 core1_sft_rst;
205 	u32 resv6[1];
206 	u32 usb_hi_addr;
207 	u32 etsecclkadjcr;
208 	u32 sai_clk;
209 	u32 resv7[1];
210 	u32 dcu_streamid;
211 	u32 usb2_streamid;
212 	u32 ftm_reset;
213 	u32 altcbar;
214 	u32 qspi_cfg;
215 	u32 pmcintecr;
216 	u32 pmcintlecr;
217 	u32 pmcintsr;
218 	u32 qos1;
219 	u32 qos2;
220 	u32 qos3;
221 	u32 cci_cfg;
222 	u32 endiancr;
223 	u32 etsecdmamcr;
224 	u32 usb3prm3cr;
225 	u32 resv9[1];
226 	u32 debug_streamid;
227 	u32 resv10[5];
228 	u32 snpcnfgcr;
229 	u32 resv11[1];
230 	u32 intpcr;
231 	u32 resv12[20];
232 	u32 scfgrevcr;
233 	u32 coresrencr;
234 	u32 pex2pmrdsr;
235 	u32 eddrtqcfg;
236 	u32 ddrc2cr;
237 	u32 ddrc3cr;
238 	u32 ddrc4cr;
239 	u32 ddrgcr;
240 	u32 resv13[120];
241 	u32 qeioclkcr;
242 	u32 etsecmcr;
243 	u32 sdhciovserlcr;
244 	u32 resv14[61];
245 	u32 sparecr[8];
246 };
247 
248 /* Clocking */
249 struct ccsr_clk {
250 	struct {
251 		u32 clkcncsr;	/* core cluster n clock control status */
252 		u8  res_004[0x1c];
253 	} clkcsr[2];
254 	u8	res_040[0x7c0]; /* 0x100 */
255 	struct {
256 		u32 pllcngsr;
257 		u8 res_804[0x1c];
258 	} pllcgsr[2];
259 	u8	res_840[0x1c0];
260 	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
261 	u8	res_a04[0x1fc];
262 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
263 	u8	res_c04[0x1c];
264 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
265 	u8	res_c24[0x3dc];
266 };
267 
268 /* System Counter */
269 struct sctr_regs {
270 	u32 cntcr;
271 	u32 cntsr;
272 	u32 cntcv1;
273 	u32 cntcv2;
274 	u32 resv1[4];
275 	u32 cntfid0;
276 	u32 cntfid1;
277 	u32 resv2[1002];
278 	u32 counterid[12];
279 };
280 
281 #define MAX_SERDES			1
282 #define SRDS_MAX_LANES			4
283 #define SRDS_MAX_BANK			2
284 
285 #define SRDS_RSTCTL_RST			0x80000000
286 #define SRDS_RSTCTL_RSTDONE		0x40000000
287 #define SRDS_RSTCTL_RSTERR		0x20000000
288 #define SRDS_RSTCTL_SWRST		0x10000000
289 #define SRDS_RSTCTL_SDEN		0x00000020
290 #define SRDS_RSTCTL_SDRST_B		0x00000040
291 #define SRDS_RSTCTL_PLLRST_B		0x00000080
292 #define SRDS_PLLCR0_POFF		0x80000000
293 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
294 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
295 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
296 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
297 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
298 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
299 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
300 #define SRDS_PLLCR0_PLL_LCK		0x00800000
301 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
302 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
303 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
304 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
305 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
306 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
307 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
308 #define SRDS_PLLCR1_PLL_BWSEL		0x08000000
309 
310 struct ccsr_serdes {
311 	struct {
312 		u32	rstctl;	/* Reset Control Register */
313 
314 		u32	pllcr0; /* PLL Control Register 0 */
315 
316 		u32	pllcr1; /* PLL Control Register 1 */
317 		u32	res_0c;	/* 0x00c */
318 		u32	pllcr3;
319 		u32	pllcr4;
320 		u8	res_18[0x20-0x18];
321 	} bank[2];
322 	u8	res_40[0x90-0x40];
323 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
324 	u8	res_94[0xa0-0x94];
325 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
326 	u8	res_a4[0xb0-0xa4];
327 	u32	srdsgr0;	/* 0xb0 General Register 0 */
328 	u8	res_b4[0xe0-0xb4];
329 	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
330 	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
331 	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
332 	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
333 	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
334 	u8	res_f4[0x100-0xf4];
335 	struct {
336 		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
337 		u8	res_104[0x120-0x104];
338 	} srdslnpssr[4];
339 	u8	res_180[0x300-0x180];
340 	u32	srdspexeqcr;
341 	u32	srdspexeqpcr[11];
342 	u8	res_330[0x400-0x330];
343 	u32	srdspexapcr;
344 	u8	res_404[0x440-0x404];
345 	u32	srdspexbpcr;
346 	u8	res_444[0x800-0x444];
347 	struct {
348 		u32	gcr0;	/* 0x800 General Control Register 0 */
349 		u32	gcr1;	/* 0x804 General Control Register 1 */
350 		u32	gcr2;	/* 0x808 General Control Register 2 */
351 		u32	sscr0;
352 		u32	recr0;	/* 0x810 Receive Equalization Control */
353 		u32	recr1;
354 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
355 		u32	sscr1;
356 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
357 		u8	res_824[0x83c-0x824];
358 		u32	tcsr3;
359 	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
360 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
361 };
362 
363 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
364 #define CCI400_CTRLORD_EN_BARRIER	0
365 #define CCI400_SHAORD_NON_SHAREABLE	0x00000002
366 #define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
367 #define CCI400_SNOOP_REQ_EN		0x00000001
368 
369 /* CCI-400 registers */
370 struct ccsr_cci400 {
371 	u32 ctrl_ord;			/* Control Override */
372 	u32 spec_ctrl;			/* Speculation Control */
373 	u32 secure_access;		/* Secure Access */
374 	u32 status;			/* Status */
375 	u32 impr_err;			/* Imprecise Error */
376 	u8 res_14[0x100 - 0x14];
377 	u32 pmcr;			/* Performance Monitor Control */
378 	u8 res_104[0xfd0 - 0x104];
379 	u32 pid[8];			/* Peripheral ID */
380 	u32 cid[4];			/* Component ID */
381 	struct {
382 		u32 snoop_ctrl;		/* Snoop Control */
383 		u32 sha_ord;		/* Shareable Override */
384 		u8 res_1008[0x1100 - 0x1008];
385 		u32 rc_qos_ord;		/* read channel QoS Value Override */
386 		u32 wc_qos_ord;		/* read channel QoS Value Override */
387 		u8 res_1108[0x110c - 0x1108];
388 		u32 qos_ctrl;		/* QoS Control */
389 		u32 max_ot;		/* Max OT */
390 		u8 res_1114[0x1130 - 0x1114];
391 		u32 target_lat;		/* Target Latency */
392 		u32 latency_regu;	/* Latency Regulation */
393 		u32 qos_range;		/* QoS Range */
394 		u8 res_113c[0x2000 - 0x113c];
395 	} slave[5];			/* Slave Interface */
396 	u8 res_6000[0x9004 - 0x6000];
397 	u32 cycle_counter;		/* Cycle counter */
398 	u32 count_ctrl;			/* Count Control */
399 	u32 overflow_status;		/* Overflow Flag Status */
400 	u8 res_9010[0xa000 - 0x9010];
401 	struct {
402 		u32 event_select;	/* Event Select */
403 		u32 event_count;	/* Event Count */
404 		u32 counter_ctrl;	/* Counter Control */
405 		u32 overflow_status;	/* Overflow Flag Status */
406 		u8 res_a010[0xb000 - 0xa010];
407 	} pcounter[4];			/* Performance Counter */
408 	u8 res_e004[0x10000 - 0xe004];
409 };
410 
411 /* AHCI (sata) register map */
412 struct ccsr_ahci {
413 	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
414 	u32 pcfg;	/* port config */
415 	u32 ppcfg;	/* port phy1 config */
416 	u32 pp2c;	/* port phy2 config */
417 	u32 pp3c;	/* port phy3 config */
418 	u32 pp4c;	/* port phy4 config */
419 	u32 pp5c;	/* port phy5 config */
420 	u32 paxic;	/* port AXI config */
421 	u32 axicc;	/* AXI cache control */
422 	u32 axipc;	/* AXI PROT control */
423 	u32 ptc;	/* port Trans Config */
424 	u32 pts;	/* port Trans Status */
425 	u32 plc;	/* port link config */
426 	u32 plc1;	/* port link config1 */
427 	u32 plc2;	/* port link config2 */
428 	u32 pls;	/* port link status */
429 	u32 pls1;	/* port link status1 */
430 	u32 pcmdc;	/* port CMD config */
431 	u32 ppcs;	/* port phy control status */
432 	u32 pberr;	/* port 0/1 BIST error */
433 	u32 cmds;	/* port 0/1 CMD status error */
434 };
435 
436 uint get_svr(void);
437 
438 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
439