1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8 #define __ASM_ARCH_LS102XA_IMMAP_H_ 9 10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14 15 #define SOC_VER_SLS1020 0x00 16 #define SOC_VER_LS1020 0x10 17 #define SOC_VER_LS1021 0x11 18 #define SOC_VER_LS1022 0x12 19 20 #define CCSR_BRR_OFFSET 0xe4 21 #define CCSR_SCRATCHRW1_OFFSET 0x200 22 23 #define RCWSR0_SYS_PLL_RAT_SHIFT 25 24 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 25 #define RCWSR0_MEM_PLL_RAT_SHIFT 16 26 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 27 28 #define RCWSR4_SRDS1_PRTCL_SHIFT 24 29 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 30 31 #define TIMER_COMP_VAL 0xffffffff 32 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 33 #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 34 35 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 36 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 37 38 #define DCFG_DCSR_PORCR1 0 39 40 struct sys_info { 41 unsigned long freq_processor[CONFIG_MAX_CPUS]; 42 unsigned long freq_systembus; 43 unsigned long freq_ddrbus; 44 unsigned long freq_localbus; 45 }; 46 47 /* Device Configuration and Pin Control */ 48 struct ccsr_gur { 49 u32 porsr1; /* POR status 1 */ 50 u32 porsr2; /* POR status 2 */ 51 u8 res_008[0x20-0x8]; 52 u32 gpporcr1; /* General-purpose POR configuration */ 53 u32 gpporcr2; 54 u32 dcfg_fusesr; /* Fuse status register */ 55 u8 res_02c[0x70-0x2c]; 56 u32 devdisr; /* Device disable control */ 57 u32 devdisr2; /* Device disable control 2 */ 58 u32 devdisr3; /* Device disable control 3 */ 59 u32 devdisr4; /* Device disable control 4 */ 60 u32 devdisr5; /* Device disable control 5 */ 61 u8 res_084[0x94-0x84]; 62 u32 coredisru; /* uppper portion for support of 64 cores */ 63 u32 coredisrl; /* lower portion for support of 64 cores */ 64 u8 res_09c[0xa4-0x9c]; 65 u32 svr; /* System version */ 66 u8 res_0a8[0xb0-0xa8]; 67 u32 rstcr; /* Reset control */ 68 u32 rstrqpblsr; /* Reset request preboot loader status */ 69 u8 res_0b8[0xc0-0xb8]; 70 u32 rstrqmr1; /* Reset request mask */ 71 u8 res_0c4[0xc8-0xc4]; 72 u32 rstrqsr1; /* Reset request status */ 73 u8 res_0cc[0xd4-0xcc]; 74 u32 rstrqwdtmrl; /* Reset request WDT mask */ 75 u8 res_0d8[0xdc-0xd8]; 76 u32 rstrqwdtsrl; /* Reset request WDT status */ 77 u8 res_0e0[0xe4-0xe0]; 78 u32 brrl; /* Boot release */ 79 u8 res_0e8[0x100-0xe8]; 80 u32 rcwsr[16]; /* Reset control word status */ 81 u8 res_140[0x200-0x140]; 82 u32 scratchrw[4]; /* Scratch Read/Write */ 83 u8 res_210[0x300-0x210]; 84 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 85 u8 res_310[0x400-0x310]; 86 u32 crstsr; 87 u8 res_404[0x550-0x404]; 88 u32 sataliodnr; 89 u8 res_554[0x604-0x554]; 90 u32 pamubypenr; 91 u32 dmacr1; 92 u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 93 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 94 struct { 95 u32 upper; 96 u32 lower; 97 } tp_cluster[1]; /* Core Cluster n Topology Register */ 98 u8 res_848[0xe60-0x848]; 99 u32 ddrclkdr; 100 u8 res_e60[0xe68-0xe64]; 101 u32 ifcclkdr; 102 u8 res_e68[0xe80-0xe6c]; 103 u32 sdhcpcr; 104 }; 105 106 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f 107 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 108 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 109 #define SCFG_QSPI_CLKSEL 0xc0100000 110 111 /* Supplemental Configuration Unit */ 112 struct ccsr_scfg { 113 u32 dpslpcr; 114 u32 resv0[2]; 115 u32 etsecclkdpslpcr; 116 u32 resv1[5]; 117 u32 fuseovrdcr; 118 u32 pixclkcr; 119 u32 resv2[5]; 120 u32 spimsicr; 121 u32 resv3[6]; 122 u32 pex1pmwrcr; 123 u32 pex1pmrdsr; 124 u32 resv4[3]; 125 u32 usb3prm1cr; 126 u32 usb4prm2cr; 127 u32 pex1rdmsgpldlsbsr; 128 u32 pex1rdmsgpldmsbsr; 129 u32 pex2rdmsgpldlsbsr; 130 u32 pex2rdmsgpldmsbsr; 131 u32 pex1rdmmsgrqsr; 132 u32 pex2rdmmsgrqsr; 133 u32 spimsiclrcr; 134 u32 pex1mscportsr; 135 u32 pex2mscportsr; 136 u32 pex2pmwrcr; 137 u32 resv5[24]; 138 u32 mac1_streamid; 139 u32 mac2_streamid; 140 u32 mac3_streamid; 141 u32 pex1_streamid; 142 u32 pex2_streamid; 143 u32 dma_streamid; 144 u32 sata_streamid; 145 u32 usb3_streamid; 146 u32 qe_streamid; 147 u32 sdhc_streamid; 148 u32 adma_streamid; 149 u32 letechsftrstcr; 150 u32 core0_sft_rst; 151 u32 core1_sft_rst; 152 u32 resv6[1]; 153 u32 usb_hi_addr; 154 u32 etsecclkadjcr; 155 u32 sai_clk; 156 u32 resv7[1]; 157 u32 dcu_streamid; 158 u32 usb2_streamid; 159 u32 ftm_reset; 160 u32 altcbar; 161 u32 qspi_cfg; 162 u32 pmcintecr; 163 u32 pmcintlecr; 164 u32 pmcintsr; 165 u32 qos1; 166 u32 qos2; 167 u32 qos3; 168 u32 cci_cfg; 169 u32 resv8[1]; 170 u32 etsecdmamcr; 171 u32 usb3prm3cr; 172 u32 resv9[1]; 173 u32 debug_streamid; 174 u32 resv10[5]; 175 u32 snpcnfgcr; 176 u32 resv11[1]; 177 u32 intpcr; 178 u32 resv12[20]; 179 u32 scfgrevcr; 180 u32 coresrencr; 181 u32 pex2pmrdsr; 182 u32 ddrc1cr; 183 u32 ddrc2cr; 184 u32 ddrc3cr; 185 u32 ddrc4cr; 186 u32 ddrgcr; 187 u32 resv13[120]; 188 u32 qeioclkcr; 189 u32 etsecmcr; 190 u32 sdhciovserlcr; 191 u32 resv14[61]; 192 u32 sparecr[8]; 193 }; 194 195 /* Clocking */ 196 struct ccsr_clk { 197 struct { 198 u32 clkcncsr; /* core cluster n clock control status */ 199 u8 res_004[0x1c]; 200 } clkcsr[2]; 201 u8 res_040[0x7c0]; /* 0x100 */ 202 struct { 203 u32 pllcngsr; 204 u8 res_804[0x1c]; 205 } pllcgsr[2]; 206 u8 res_840[0x1c0]; 207 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 208 u8 res_a04[0x1fc]; 209 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 210 u8 res_c04[0x1c]; 211 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 212 u8 res_c24[0x3dc]; 213 }; 214 215 /* System Counter */ 216 struct sctr_regs { 217 u32 cntcr; 218 u32 cntsr; 219 u32 cntcv1; 220 u32 cntcv2; 221 u32 resv1[4]; 222 u32 cntfid0; 223 u32 cntfid1; 224 u32 resv2[1002]; 225 u32 counterid[12]; 226 }; 227 228 #define MAX_SERDES 1 229 #define SRDS_MAX_LANES 4 230 #define SRDS_MAX_BANK 2 231 232 #define SRDS_RSTCTL_RST 0x80000000 233 #define SRDS_RSTCTL_RSTDONE 0x40000000 234 #define SRDS_RSTCTL_RSTERR 0x20000000 235 #define SRDS_RSTCTL_SWRST 0x10000000 236 #define SRDS_RSTCTL_SDEN 0x00000020 237 #define SRDS_RSTCTL_SDRST_B 0x00000040 238 #define SRDS_RSTCTL_PLLRST_B 0x00000080 239 #define SRDS_PLLCR0_POFF 0x80000000 240 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 241 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 242 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 243 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 244 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 245 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 246 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 247 #define SRDS_PLLCR0_PLL_LCK 0x00800000 248 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 249 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 250 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 251 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 252 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 253 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 254 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 255 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 256 257 struct ccsr_serdes { 258 struct { 259 u32 rstctl; /* Reset Control Register */ 260 261 u32 pllcr0; /* PLL Control Register 0 */ 262 263 u32 pllcr1; /* PLL Control Register 1 */ 264 u32 res_0c; /* 0x00c */ 265 u32 pllcr3; 266 u32 pllcr4; 267 u8 res_18[0x20-0x18]; 268 } bank[2]; 269 u8 res_40[0x90-0x40]; 270 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 271 u8 res_94[0xa0-0x94]; 272 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 273 u8 res_a4[0xb0-0xa4]; 274 u32 srdsgr0; /* 0xb0 General Register 0 */ 275 u8 res_b4[0xe0-0xb4]; 276 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 277 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 278 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 279 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 280 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 281 u8 res_f4[0x100-0xf4]; 282 struct { 283 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 284 u8 res_104[0x120-0x104]; 285 } srdslnpssr[4]; 286 u8 res_180[0x300-0x180]; 287 u32 srdspexeqcr; 288 u32 srdspexeqpcr[11]; 289 u8 res_330[0x400-0x330]; 290 u32 srdspexapcr; 291 u8 res_404[0x440-0x404]; 292 u32 srdspexbpcr; 293 u8 res_444[0x800-0x444]; 294 struct { 295 u32 gcr0; /* 0x800 General Control Register 0 */ 296 u32 gcr1; /* 0x804 General Control Register 1 */ 297 u32 gcr2; /* 0x808 General Control Register 2 */ 298 u32 sscr0; 299 u32 recr0; /* 0x810 Receive Equalization Control */ 300 u32 recr1; 301 u32 tecr0; /* 0x818 Transmit Equalization Control */ 302 u32 sscr1; 303 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 304 u8 res_824[0x83c-0x824]; 305 u32 tcsr3; 306 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 307 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 308 }; 309 310 #define DDR_SDRAM_CFG 0x470c0008 311 #define DDR_CS0_BNDS 0x008000bf 312 #define DDR_CS0_CONFIG 0x80014302 313 #define DDR_TIMING_CFG_0 0x50550004 314 #define DDR_TIMING_CFG_1 0xbcb38c56 315 #define DDR_TIMING_CFG_2 0x0040d120 316 #define DDR_TIMING_CFG_3 0x010e1000 317 #define DDR_TIMING_CFG_4 0x00000001 318 #define DDR_TIMING_CFG_5 0x03401400 319 #define DDR_SDRAM_CFG_2 0x00401010 320 #define DDR_SDRAM_MODE 0x00061c60 321 #define DDR_SDRAM_MODE_2 0x00180000 322 #define DDR_SDRAM_INTERVAL 0x18600618 323 #define DDR_DDR_WRLVL_CNTL 0x8655f605 324 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 325 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 326 #define DDR_DDR_CDR1 0x80040000 327 #define DDR_DDR_CDR2 0x00000001 328 #define DDR_SDRAM_CLK_CNTL 0x02000000 329 #define DDR_DDR_ZQ_CNTL 0x89080600 330 #define DDR_CS0_CONFIG_2 0 331 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 332 333 /* DDR memory controller registers */ 334 struct ccsr_ddr { 335 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 336 u32 resv1[1]; 337 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 338 u32 resv2[1]; 339 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 340 u32 resv3[1]; 341 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 342 u32 resv4[25]; 343 u32 cs0_config; /* Chip Select Configuration */ 344 u32 cs1_config; /* Chip Select Configuration */ 345 u32 cs2_config; /* Chip Select Configuration */ 346 u32 cs3_config; /* Chip Select Configuration */ 347 u32 resv5[12]; 348 u32 cs0_config_2; /* Chip Select Configuration 2 */ 349 u32 cs1_config_2; /* Chip Select Configuration 2 */ 350 u32 cs2_config_2; /* Chip Select Configuration 2 */ 351 u32 cs3_config_2; /* Chip Select Configuration 2 */ 352 u32 resv6[12]; 353 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 354 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 355 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 356 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 357 u32 sdram_cfg; /* SDRAM Control Configuration */ 358 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 359 u32 sdram_mode; /* SDRAM Mode Configuration */ 360 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 361 u32 sdram_md_cntl; /* SDRAM Mode Control */ 362 u32 sdram_interval; /* SDRAM Interval Configuration */ 363 u32 sdram_data_init; /* SDRAM Data initialization */ 364 u32 resv7[1]; 365 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 366 u32 resv8[5]; 367 u32 init_addr; /* training init addr */ 368 u32 init_ext_addr; /* training init extended addr */ 369 u32 resv9[4]; 370 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 371 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 372 u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ 373 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ 374 u32 ddr_zq_cntl; /* ZQ calibration control*/ 375 u32 ddr_wrlvl_cntl; /* write leveling control*/ 376 u32 resv10[1]; 377 u32 ddr_sr_cntr; /* self refresvh counter */ 378 u32 ddr_sdram_rcw_1; /* Control Words 1 */ 379 u32 ddr_sdram_rcw_2; /* Control Words 2 */ 380 u32 resv11[2]; 381 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 382 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 383 u32 resv12[2]; 384 u32 ddr_sdram_rcw_3; /* Control Words 3 */ 385 u32 ddr_sdram_rcw_4; /* Control Words 4 */ 386 u32 ddr_sdram_rcw_5; /* Control Words 5 */ 387 u32 ddr_sdram_rcw_6; /* Control Words 6 */ 388 u32 resv13[20]; 389 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 390 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 391 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 392 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 393 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 394 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 395 u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ 396 u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ 397 u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ 398 u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ 399 u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ 400 u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ 401 u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ 402 u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ 403 u32 resv14[4]; 404 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ 405 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ 406 u32 resv15[2]; 407 u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */ 408 u32 resv16[15]; 409 u32 deskew_cntl; /* SDRAM Deskew Control */ 410 u32 resv17[545]; 411 u32 ddr_dsr1; /* Debug Status 1 */ 412 u32 ddr_dsr2; /* Debug Status 2 */ 413 u32 ddr_cdr1; /* Control Driver 1 */ 414 u32 ddr_cdr2; /* Control Driver 2 */ 415 u32 resv18[50]; 416 u32 ip_rev1; /* IP Block Revision 1 */ 417 u32 ip_rev2; /* IP Block Revision 2 */ 418 u32 eor; /* Enhanced Optimization Register */ 419 u32 resv19[63]; 420 u32 mtcr; /* Memory Test Control Register */ 421 u32 resv20[7]; 422 u32 mtp1; /* Memory Test Pattern 1 */ 423 u32 mtp2; /* Memory Test Pattern 2 */ 424 u32 mtp3; /* Memory Test Pattern 3 */ 425 u32 mtp4; /* Memory Test Pattern 4 */ 426 u32 mtp5; /* Memory Test Pattern 5 */ 427 u32 mtp6; /* Memory Test Pattern 6 */ 428 u32 mtp7; /* Memory Test Pattern 7 */ 429 u32 mtp8; /* Memory Test Pattern 8 */ 430 u32 mtp9; /* Memory Test Pattern 9 */ 431 u32 mtp10; /* Memory Test Pattern 10 */ 432 u32 resv21[6]; 433 u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */ 434 u32 ddr_mt_st_addr; /* Memory Test Start Address */ 435 u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */ 436 u32 ddr_mt_end_addr; /* Memory Test End Address */ 437 u32 resv22[36]; 438 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 439 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 440 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 441 u32 resv23[5]; 442 u32 capture_data_hi; /* Data Path Read Capture High */ 443 u32 capture_data_lo; /* Data Path Read Capture Low */ 444 u32 capture_ecc; /* Data Path Read Capture ECC */ 445 u32 resv24[5]; 446 u32 err_detect; /* Error Detect */ 447 u32 err_disable; /* Error Disable */ 448 u32 err_int_en; 449 u32 capture_attributes; /* Error Attrs Capture */ 450 u32 capture_address; /* Error Addr Capture */ 451 u32 capture_ext_address; /* Error Extended Addr Capture */ 452 u32 err_sbe; /* Single-Bit ECC Error Management */ 453 u32 resv25[105]; 454 }; 455 456 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 457 #define CCI400_CTRLORD_EN_BARRIER 0 458 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 459 460 /* CCI-400 registers */ 461 struct ccsr_cci400 { 462 u32 ctrl_ord; /* Control Override */ 463 u32 spec_ctrl; /* Speculation Control */ 464 u32 secure_access; /* Secure Access */ 465 u32 status; /* Status */ 466 u32 impr_err; /* Imprecise Error */ 467 u8 res_14[0x100 - 0x14]; 468 u32 pmcr; /* Performance Monitor Control */ 469 u8 res_104[0xfd0 - 0x104]; 470 u32 pid[8]; /* Peripheral ID */ 471 u32 cid[4]; /* Component ID */ 472 struct { 473 u32 snoop_ctrl; /* Snoop Control */ 474 u32 sha_ord; /* Shareable Override */ 475 u8 res_1008[0x1100 - 0x1008]; 476 u32 rc_qos_ord; /* read channel QoS Value Override */ 477 u32 wc_qos_ord; /* read channel QoS Value Override */ 478 u8 res_1108[0x110c - 0x1108]; 479 u32 qos_ctrl; /* QoS Control */ 480 u32 max_ot; /* Max OT */ 481 u8 res_1114[0x1130 - 0x1114]; 482 u32 target_lat; /* Target Latency */ 483 u32 latency_regu; /* Latency Regulation */ 484 u32 qos_range; /* QoS Range */ 485 u8 res_113c[0x2000 - 0x113c]; 486 } slave[5]; /* Slave Interface */ 487 u8 res_6000[0x9004 - 0x6000]; 488 u32 cycle_counter; /* Cycle counter */ 489 u32 count_ctrl; /* Count Control */ 490 u32 overflow_status; /* Overflow Flag Status */ 491 u8 res_9010[0xa000 - 0x9010]; 492 struct { 493 u32 event_select; /* Event Select */ 494 u32 event_count; /* Event Count */ 495 u32 counter_ctrl; /* Counter Control */ 496 u32 overflow_status; /* Overflow Flag Status */ 497 u8 res_a010[0xb000 - 0xa010]; 498 } pcounter[4]; /* Performance Counter */ 499 u8 res_e004[0x10000 - 0xe004]; 500 }; 501 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 502