1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8 #define __ASM_ARCH_LS102XA_IMMAP_H_ 9 10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14 15 #define SOC_VER_SLS1020 0x00 16 #define SOC_VER_LS1020 0x10 17 #define SOC_VER_LS1021 0x11 18 #define SOC_VER_LS1022 0x12 19 20 #define RCWSR0_SYS_PLL_RAT_SHIFT 25 21 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 22 #define RCWSR0_MEM_PLL_RAT_SHIFT 16 23 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 24 25 #define RCWSR4_SRDS1_PRTCL_SHIFT 24 26 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 27 28 #define TIMER_COMP_VAL 0xffffffff 29 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 30 #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 31 32 struct sys_info { 33 unsigned long freq_processor[CONFIG_MAX_CPUS]; 34 unsigned long freq_systembus; 35 unsigned long freq_ddrbus; 36 unsigned long freq_localbus; 37 }; 38 39 /* Device Configuration and Pin Control */ 40 struct ccsr_gur { 41 u32 porsr1; /* POR status 1 */ 42 u32 porsr2; /* POR status 2 */ 43 u8 res_008[0x20-0x8]; 44 u32 gpporcr1; /* General-purpose POR configuration */ 45 u32 gpporcr2; 46 u32 dcfg_fusesr; /* Fuse status register */ 47 u8 res_02c[0x70-0x2c]; 48 u32 devdisr; /* Device disable control */ 49 u32 devdisr2; /* Device disable control 2 */ 50 u32 devdisr3; /* Device disable control 3 */ 51 u32 devdisr4; /* Device disable control 4 */ 52 u32 devdisr5; /* Device disable control 5 */ 53 u8 res_084[0x94-0x84]; 54 u32 coredisru; /* uppper portion for support of 64 cores */ 55 u32 coredisrl; /* lower portion for support of 64 cores */ 56 u8 res_09c[0xa4-0x9c]; 57 u32 svr; /* System version */ 58 u8 res_0a8[0xb0-0xa8]; 59 u32 rstcr; /* Reset control */ 60 u32 rstrqpblsr; /* Reset request preboot loader status */ 61 u8 res_0b8[0xc0-0xb8]; 62 u32 rstrqmr1; /* Reset request mask */ 63 u8 res_0c4[0xc8-0xc4]; 64 u32 rstrqsr1; /* Reset request status */ 65 u8 res_0cc[0xd4-0xcc]; 66 u32 rstrqwdtmrl; /* Reset request WDT mask */ 67 u8 res_0d8[0xdc-0xd8]; 68 u32 rstrqwdtsrl; /* Reset request WDT status */ 69 u8 res_0e0[0xe4-0xe0]; 70 u32 brrl; /* Boot release */ 71 u8 res_0e8[0x100-0xe8]; 72 u32 rcwsr[16]; /* Reset control word status */ 73 u8 res_140[0x200-0x140]; 74 u32 scratchrw[4]; /* Scratch Read/Write */ 75 u8 res_210[0x300-0x210]; 76 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 77 u8 res_310[0x400-0x310]; 78 u32 crstsr; 79 u8 res_404[0x550-0x404]; 80 u32 sataliodnr; 81 u8 res_554[0x604-0x554]; 82 u32 pamubypenr; 83 u32 dmacr1; 84 u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 85 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 86 struct { 87 u32 upper; 88 u32 lower; 89 } tp_cluster[1]; /* Core Cluster n Topology Register */ 90 u8 res_848[0xe60-0x848]; 91 u32 ddrclkdr; 92 u8 res_e60[0xe68-0xe64]; 93 u32 ifcclkdr; 94 u8 res_e68[0xe80-0xe6c]; 95 u32 sdhcpcr; 96 }; 97 98 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f 99 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 100 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 101 102 /* Supplemental Configuration Unit */ 103 struct ccsr_scfg { 104 u32 dpslpcr; 105 u32 resv0[2]; 106 u32 etsecclkdpslpcr; 107 u32 resv1[5]; 108 u32 fuseovrdcr; 109 u32 pixclkcr; 110 u32 resv2[5]; 111 u32 spimsicr; 112 u32 resv3[6]; 113 u32 pex1pmwrcr; 114 u32 pex1pmrdsr; 115 u32 resv4[3]; 116 u32 usb3prm1cr; 117 u32 usb4prm2cr; 118 u32 pex1rdmsgpldlsbsr; 119 u32 pex1rdmsgpldmsbsr; 120 u32 pex2rdmsgpldlsbsr; 121 u32 pex2rdmsgpldmsbsr; 122 u32 pex1rdmmsgrqsr; 123 u32 pex2rdmmsgrqsr; 124 u32 spimsiclrcr; 125 u32 pex1mscportsr; 126 u32 pex2mscportsr; 127 u32 pex2pmwrcr; 128 u32 resv5[24]; 129 u32 mac1_streamid; 130 u32 mac2_streamid; 131 u32 mac3_streamid; 132 u32 pex1_streamid; 133 u32 pex2_streamid; 134 u32 dma_streamid; 135 u32 sata_streamid; 136 u32 usb3_streamid; 137 u32 qe_streamid; 138 u32 sdhc_streamid; 139 u32 adma_streamid; 140 u32 letechsftrstcr; 141 u32 core0_sft_rst; 142 u32 core1_sft_rst; 143 u32 resv6[1]; 144 u32 usb_hi_addr; 145 u32 etsecclkadjcr; 146 u32 sai_clk; 147 u32 resv7[1]; 148 u32 dcu_streamid; 149 u32 usb2_streamid; 150 u32 ftm_reset; 151 u32 altcbar; 152 u32 qspi_cfg; 153 u32 pmcintecr; 154 u32 pmcintlecr; 155 u32 pmcintsr; 156 u32 qos1; 157 u32 qos2; 158 u32 qos3; 159 u32 cci_cfg; 160 u32 resv8[1]; 161 u32 etsecdmamcr; 162 u32 usb3prm3cr; 163 u32 resv9[1]; 164 u32 debug_streamid; 165 u32 resv10[5]; 166 u32 snpcnfgcr; 167 u32 resv11[1]; 168 u32 intpcr; 169 u32 resv12[20]; 170 u32 scfgrevcr; 171 u32 coresrencr; 172 u32 pex2pmrdsr; 173 u32 ddrc1cr; 174 u32 ddrc2cr; 175 u32 ddrc3cr; 176 u32 ddrc4cr; 177 u32 ddrgcr; 178 u32 resv13[120]; 179 u32 qeioclkcr; 180 u32 etsecmcr; 181 u32 sdhciovserlcr; 182 u32 resv14[61]; 183 u32 sparecr[8]; 184 }; 185 186 /* Clocking */ 187 struct ccsr_clk { 188 struct { 189 u32 clkcncsr; /* core cluster n clock control status */ 190 u8 res_004[0x1c]; 191 } clkcsr[2]; 192 u8 res_040[0x7c0]; /* 0x100 */ 193 struct { 194 u32 pllcngsr; 195 u8 res_804[0x1c]; 196 } pllcgsr[2]; 197 u8 res_840[0x1c0]; 198 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 199 u8 res_a04[0x1fc]; 200 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 201 u8 res_c04[0x1c]; 202 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 203 u8 res_c24[0x3dc]; 204 }; 205 206 /* System Counter */ 207 struct sctr_regs { 208 u32 cntcr; 209 u32 cntsr; 210 u32 cntcv1; 211 u32 cntcv2; 212 u32 resv1[4]; 213 u32 cntfid0; 214 u32 cntfid1; 215 u32 resv2[1002]; 216 u32 counterid[12]; 217 }; 218 219 #define MAX_SERDES 1 220 #define SRDS_MAX_LANES 4 221 #define SRDS_MAX_BANK 2 222 223 #define SRDS_RSTCTL_RST 0x80000000 224 #define SRDS_RSTCTL_RSTDONE 0x40000000 225 #define SRDS_RSTCTL_RSTERR 0x20000000 226 #define SRDS_RSTCTL_SWRST 0x10000000 227 #define SRDS_RSTCTL_SDEN 0x00000020 228 #define SRDS_RSTCTL_SDRST_B 0x00000040 229 #define SRDS_RSTCTL_PLLRST_B 0x00000080 230 #define SRDS_PLLCR0_POFF 0x80000000 231 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 232 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 233 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 234 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 235 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 236 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 237 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 238 #define SRDS_PLLCR0_PLL_LCK 0x00800000 239 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 240 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 241 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 242 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 243 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 244 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 245 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 246 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 247 248 struct ccsr_serdes { 249 struct { 250 u32 rstctl; /* Reset Control Register */ 251 252 u32 pllcr0; /* PLL Control Register 0 */ 253 254 u32 pllcr1; /* PLL Control Register 1 */ 255 u32 res_0c; /* 0x00c */ 256 u32 pllcr3; 257 u32 pllcr4; 258 u8 res_18[0x20-0x18]; 259 } bank[2]; 260 u8 res_40[0x90-0x40]; 261 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 262 u8 res_94[0xa0-0x94]; 263 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 264 u8 res_a4[0xb0-0xa4]; 265 u32 srdsgr0; /* 0xb0 General Register 0 */ 266 u8 res_b4[0xe0-0xb4]; 267 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 268 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 269 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 270 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 271 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 272 u8 res_f4[0x100-0xf4]; 273 struct { 274 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 275 u8 res_104[0x120-0x104]; 276 } srdslnpssr[4]; 277 u8 res_180[0x300-0x180]; 278 u32 srdspexeqcr; 279 u32 srdspexeqpcr[11]; 280 u8 res_330[0x400-0x330]; 281 u32 srdspexapcr; 282 u8 res_404[0x440-0x404]; 283 u32 srdspexbpcr; 284 u8 res_444[0x800-0x444]; 285 struct { 286 u32 gcr0; /* 0x800 General Control Register 0 */ 287 u32 gcr1; /* 0x804 General Control Register 1 */ 288 u32 gcr2; /* 0x808 General Control Register 2 */ 289 u32 sscr0; 290 u32 recr0; /* 0x810 Receive Equalization Control */ 291 u32 recr1; 292 u32 tecr0; /* 0x818 Transmit Equalization Control */ 293 u32 sscr1; 294 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 295 u8 res_824[0x83c-0x824]; 296 u32 tcsr3; 297 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 298 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 299 }; 300 301 #define DDR_SDRAM_CFG 0x470c0008 302 #define DDR_CS0_BNDS 0x008000bf 303 #define DDR_CS0_CONFIG 0x80014302 304 #define DDR_TIMING_CFG_0 0x50550004 305 #define DDR_TIMING_CFG_1 0xbcb38c56 306 #define DDR_TIMING_CFG_2 0x0040d120 307 #define DDR_TIMING_CFG_3 0x010e1000 308 #define DDR_TIMING_CFG_4 0x00000001 309 #define DDR_TIMING_CFG_5 0x03401400 310 #define DDR_SDRAM_CFG_2 0x00401010 311 #define DDR_SDRAM_MODE 0x00061c60 312 #define DDR_SDRAM_MODE_2 0x00180000 313 #define DDR_SDRAM_INTERVAL 0x18600618 314 #define DDR_DDR_WRLVL_CNTL 0x8655f605 315 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 316 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 317 #define DDR_DDR_CDR1 0x80040000 318 #define DDR_DDR_CDR2 0x00000001 319 #define DDR_SDRAM_CLK_CNTL 0x02000000 320 #define DDR_DDR_ZQ_CNTL 0x89080600 321 #define DDR_CS0_CONFIG_2 0 322 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 323 324 /* DDR memory controller registers */ 325 struct ccsr_ddr { 326 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 327 u32 resv1[1]; 328 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 329 u32 resv2[1]; 330 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 331 u32 resv3[1]; 332 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 333 u32 resv4[25]; 334 u32 cs0_config; /* Chip Select Configuration */ 335 u32 cs1_config; /* Chip Select Configuration */ 336 u32 cs2_config; /* Chip Select Configuration */ 337 u32 cs3_config; /* Chip Select Configuration */ 338 u32 resv5[12]; 339 u32 cs0_config_2; /* Chip Select Configuration 2 */ 340 u32 cs1_config_2; /* Chip Select Configuration 2 */ 341 u32 cs2_config_2; /* Chip Select Configuration 2 */ 342 u32 cs3_config_2; /* Chip Select Configuration 2 */ 343 u32 resv6[12]; 344 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 345 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 346 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 347 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 348 u32 sdram_cfg; /* SDRAM Control Configuration */ 349 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 350 u32 sdram_mode; /* SDRAM Mode Configuration */ 351 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 352 u32 sdram_md_cntl; /* SDRAM Mode Control */ 353 u32 sdram_interval; /* SDRAM Interval Configuration */ 354 u32 sdram_data_init; /* SDRAM Data initialization */ 355 u32 resv7[1]; 356 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 357 u32 resv8[5]; 358 u32 init_addr; /* training init addr */ 359 u32 init_ext_addr; /* training init extended addr */ 360 u32 resv9[4]; 361 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 362 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 363 u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ 364 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ 365 u32 ddr_zq_cntl; /* ZQ calibration control*/ 366 u32 ddr_wrlvl_cntl; /* write leveling control*/ 367 u32 resv10[1]; 368 u32 ddr_sr_cntr; /* self refresvh counter */ 369 u32 ddr_sdram_rcw_1; /* Control Words 1 */ 370 u32 ddr_sdram_rcw_2; /* Control Words 2 */ 371 u32 resv11[2]; 372 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 373 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 374 u32 resv12[2]; 375 u32 ddr_sdram_rcw_3; /* Control Words 3 */ 376 u32 ddr_sdram_rcw_4; /* Control Words 4 */ 377 u32 ddr_sdram_rcw_5; /* Control Words 5 */ 378 u32 ddr_sdram_rcw_6; /* Control Words 6 */ 379 u32 resv13[20]; 380 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 381 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 382 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 383 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 384 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 385 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 386 u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ 387 u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ 388 u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ 389 u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ 390 u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ 391 u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ 392 u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ 393 u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ 394 u32 resv14[4]; 395 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ 396 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ 397 u32 resv15[2]; 398 u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */ 399 u32 resv16[15]; 400 u32 deskew_cntl; /* SDRAM Deskew Control */ 401 u32 resv17[545]; 402 u32 ddr_dsr1; /* Debug Status 1 */ 403 u32 ddr_dsr2; /* Debug Status 2 */ 404 u32 ddr_cdr1; /* Control Driver 1 */ 405 u32 ddr_cdr2; /* Control Driver 2 */ 406 u32 resv18[50]; 407 u32 ip_rev1; /* IP Block Revision 1 */ 408 u32 ip_rev2; /* IP Block Revision 2 */ 409 u32 eor; /* Enhanced Optimization Register */ 410 u32 resv19[63]; 411 u32 mtcr; /* Memory Test Control Register */ 412 u32 resv20[7]; 413 u32 mtp1; /* Memory Test Pattern 1 */ 414 u32 mtp2; /* Memory Test Pattern 2 */ 415 u32 mtp3; /* Memory Test Pattern 3 */ 416 u32 mtp4; /* Memory Test Pattern 4 */ 417 u32 mtp5; /* Memory Test Pattern 5 */ 418 u32 mtp6; /* Memory Test Pattern 6 */ 419 u32 mtp7; /* Memory Test Pattern 7 */ 420 u32 mtp8; /* Memory Test Pattern 8 */ 421 u32 mtp9; /* Memory Test Pattern 9 */ 422 u32 mtp10; /* Memory Test Pattern 10 */ 423 u32 resv21[6]; 424 u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */ 425 u32 ddr_mt_st_addr; /* Memory Test Start Address */ 426 u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */ 427 u32 ddr_mt_end_addr; /* Memory Test End Address */ 428 u32 resv22[36]; 429 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 430 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 431 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 432 u32 resv23[5]; 433 u32 capture_data_hi; /* Data Path Read Capture High */ 434 u32 capture_data_lo; /* Data Path Read Capture Low */ 435 u32 capture_ecc; /* Data Path Read Capture ECC */ 436 u32 resv24[5]; 437 u32 err_detect; /* Error Detect */ 438 u32 err_disable; /* Error Disable */ 439 u32 err_int_en; 440 u32 capture_attributes; /* Error Attrs Capture */ 441 u32 capture_address; /* Error Addr Capture */ 442 u32 capture_ext_address; /* Error Extended Addr Capture */ 443 u32 err_sbe; /* Single-Bit ECC Error Management */ 444 u32 resv25[105]; 445 }; 446 447 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 448 #define CCI400_CTRLORD_EN_BARRIER 0 449 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 450 451 /* CCI-400 registers */ 452 struct ccsr_cci400 { 453 u32 ctrl_ord; /* Control Override */ 454 u32 spec_ctrl; /* Speculation Control */ 455 u32 secure_access; /* Secure Access */ 456 u32 status; /* Status */ 457 u32 impr_err; /* Imprecise Error */ 458 u8 res_14[0x100 - 0x14]; 459 u32 pmcr; /* Performance Monitor Control */ 460 u8 res_104[0xfd0 - 0x104]; 461 u32 pid[8]; /* Peripheral ID */ 462 u32 cid[4]; /* Component ID */ 463 struct { 464 u32 snoop_ctrl; /* Snoop Control */ 465 u32 sha_ord; /* Shareable Override */ 466 u8 res_1008[0x1100 - 0x1008]; 467 u32 rc_qos_ord; /* read channel QoS Value Override */ 468 u32 wc_qos_ord; /* read channel QoS Value Override */ 469 u8 res_1108[0x110c - 0x1108]; 470 u32 qos_ctrl; /* QoS Control */ 471 u32 max_ot; /* Max OT */ 472 u8 res_1114[0x1130 - 0x1114]; 473 u32 target_lat; /* Target Latency */ 474 u32 latency_regu; /* Latency Regulation */ 475 u32 qos_range; /* QoS Range */ 476 u8 res_113c[0x2000 - 0x113c]; 477 } slave[5]; /* Slave Interface */ 478 u8 res_6000[0x9004 - 0x6000]; 479 u32 cycle_counter; /* Cycle counter */ 480 u32 count_ctrl; /* Count Control */ 481 u32 overflow_status; /* Overflow Flag Status */ 482 u8 res_9010[0xa000 - 0x9010]; 483 struct { 484 u32 event_select; /* Event Select */ 485 u32 event_count; /* Event Count */ 486 u32 counter_ctrl; /* Counter Control */ 487 u32 overflow_status; /* Overflow Flag Status */ 488 u8 res_a010[0xb000 - 0xa010]; 489 } pcounter[4]; /* Performance Counter */ 490 u8 res_e004[0x10000 - 0xe004]; 491 }; 492 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 493