1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 #define __ASM_ARCH_LS102XA_IMMAP_H_
9 
10 #define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
11 #define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
12 #define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
14 
15 #define SOC_VER_SLS1020		0x00
16 #define SOC_VER_LS1020		0x10
17 #define SOC_VER_LS1021		0x11
18 #define SOC_VER_LS1022		0x12
19 
20 #define SOC_MAJOR_VER_1_0	0x1
21 #define SOC_MAJOR_VER_2_0	0x2
22 
23 #define CCSR_BRR_OFFSET		0xe4
24 #define CCSR_SCRATCHRW1_OFFSET	0x200
25 
26 #define RCWSR0_SYS_PLL_RAT_SHIFT	25
27 #define RCWSR0_SYS_PLL_RAT_MASK		0x1f
28 #define RCWSR0_MEM_PLL_RAT_SHIFT	16
29 #define RCWSR0_MEM_PLL_RAT_MASK		0x3f
30 
31 #define RCWSR4_SRDS1_PRTCL_SHIFT	24
32 #define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
33 
34 #define TIMER_COMP_VAL			0xffffffff
35 #define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
36 #define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
37 
38 #define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
39 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
40 
41 #define DCFG_DCSR_PORCR1		0
42 
43 /*
44  * Define default values for some CCSR macros to make header files cleaner
45  *
46  * To completely disable CCSR relocation in a board header file, define
47  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
48  * to a value that is the same as CONFIG_SYS_CCSRBAR.
49  */
50 
51 #ifdef CONFIG_SYS_CCSRBAR_PHYS
52 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
53 #endif
54 
55 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
56 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
57 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
58 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
59 #endif
60 
61 #ifndef CONFIG_SYS_CCSRBAR
62 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
63 #endif
64 
65 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
66 #ifdef CONFIG_PHYS_64BIT
67 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
68 #else
69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
70 #endif
71 #endif
72 
73 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
75 #endif
76 
77 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
78 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
79 
80 struct sys_info {
81 	unsigned long freq_processor[CONFIG_MAX_CPUS];
82 	unsigned long freq_systembus;
83 	unsigned long freq_ddrbus;
84 	unsigned long freq_localbus;
85 };
86 
87 /* Device Configuration and Pin Control */
88 struct ccsr_gur {
89 	u32     porsr1;         /* POR status 1 */
90 	u32     porsr2;         /* POR status 2 */
91 	u8      res_008[0x20-0x8];
92 	u32     gpporcr1;       /* General-purpose POR configuration */
93 	u32	gpporcr2;
94 	u32     dcfg_fusesr;    /* Fuse status register */
95 	u8      res_02c[0x70-0x2c];
96 	u32     devdisr;        /* Device disable control */
97 	u32     devdisr2;       /* Device disable control 2 */
98 	u32     devdisr3;       /* Device disable control 3 */
99 	u32     devdisr4;       /* Device disable control 4 */
100 	u32     devdisr5;       /* Device disable control 5 */
101 	u8      res_084[0x94-0x84];
102 	u32     coredisru;      /* uppper portion for support of 64 cores */
103 	u32     coredisrl;      /* lower portion for support of 64 cores */
104 	u8      res_09c[0xa4-0x9c];
105 	u32     svr;            /* System version */
106 	u8	res_0a8[0xb0-0xa8];
107 	u32	rstcr;		/* Reset control */
108 	u32	rstrqpblsr;	/* Reset request preboot loader status */
109 	u8	res_0b8[0xc0-0xb8];
110 	u32	rstrqmr1;	/* Reset request mask */
111 	u8	res_0c4[0xc8-0xc4];
112 	u32	rstrqsr1;	/* Reset request status */
113 	u8	res_0cc[0xd4-0xcc];
114 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
115 	u8	res_0d8[0xdc-0xd8];
116 	u32	rstrqwdtsrl;	/* Reset request WDT status */
117 	u8	res_0e0[0xe4-0xe0];
118 	u32	brrl;		/* Boot release */
119 	u8      res_0e8[0x100-0xe8];
120 	u32     rcwsr[16];      /* Reset control word status */
121 	u8      res_140[0x200-0x140];
122 	u32     scratchrw[4];  /* Scratch Read/Write */
123 	u8      res_210[0x300-0x210];
124 	u32     scratchw1r[4];  /* Scratch Read (Write once) */
125 	u8      res_310[0x400-0x310];
126 	u32	crstsr;
127 	u8      res_404[0x550-0x404];
128 	u32	sataliodnr;
129 	u8	res_554[0x604-0x554];
130 	u32	pamubypenr;
131 	u32	dmacr1;
132 	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
133 	u32     tp_ityp[64];    /* Topology Initiator Type Register */
134 	struct {
135 		u32     upper;
136 		u32     lower;
137 	} tp_cluster[1];        /* Core Cluster n Topology Register */
138 	u8	res_848[0xe60-0x848];
139 	u32	ddrclkdr;
140 	u8	res_e60[0xe68-0xe64];
141 	u32	ifcclkdr;
142 	u8	res_e68[0xe80-0xe6c];
143 	u32	sdhcpcr;
144 };
145 
146 #define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
147 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
148 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
149 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
150 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
151 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
152 #define SCFG_QSPI_CLKSEL		0xc0100000
153 #define SCFG_ENDIANCR_LE		0x80000000
154 
155 /* Supplemental Configuration Unit */
156 struct ccsr_scfg {
157 	u32 dpslpcr;
158 	u32 resv0[2];
159 	u32 etsecclkdpslpcr;
160 	u32 resv1[5];
161 	u32 fuseovrdcr;
162 	u32 pixclkcr;
163 	u32 resv2[5];
164 	u32 spimsicr;
165 	u32 resv3[6];
166 	u32 pex1pmwrcr;
167 	u32 pex1pmrdsr;
168 	u32 resv4[3];
169 	u32 usb3prm1cr;
170 	u32 usb4prm2cr;
171 	u32 pex1rdmsgpldlsbsr;
172 	u32 pex1rdmsgpldmsbsr;
173 	u32 pex2rdmsgpldlsbsr;
174 	u32 pex2rdmsgpldmsbsr;
175 	u32 pex1rdmmsgrqsr;
176 	u32 pex2rdmmsgrqsr;
177 	u32 spimsiclrcr;
178 	u32 pexmscportsr[2];
179 	u32 pex2pmwrcr;
180 	u32 resv5[24];
181 	u32 mac1_streamid;
182 	u32 mac2_streamid;
183 	u32 mac3_streamid;
184 	u32 pex1_streamid;
185 	u32 pex2_streamid;
186 	u32 dma_streamid;
187 	u32 sata_streamid;
188 	u32 usb3_streamid;
189 	u32 qe_streamid;
190 	u32 sdhc_streamid;
191 	u32 adma_streamid;
192 	u32 letechsftrstcr;
193 	u32 core0_sft_rst;
194 	u32 core1_sft_rst;
195 	u32 resv6[1];
196 	u32 usb_hi_addr;
197 	u32 etsecclkadjcr;
198 	u32 sai_clk;
199 	u32 resv7[1];
200 	u32 dcu_streamid;
201 	u32 usb2_streamid;
202 	u32 ftm_reset;
203 	u32 altcbar;
204 	u32 qspi_cfg;
205 	u32 pmcintecr;
206 	u32 pmcintlecr;
207 	u32 pmcintsr;
208 	u32 qos1;
209 	u32 qos2;
210 	u32 qos3;
211 	u32 cci_cfg;
212 	u32 endiancr;
213 	u32 etsecdmamcr;
214 	u32 usb3prm3cr;
215 	u32 resv9[1];
216 	u32 debug_streamid;
217 	u32 resv10[5];
218 	u32 snpcnfgcr;
219 	u32 resv11[1];
220 	u32 intpcr;
221 	u32 resv12[20];
222 	u32 scfgrevcr;
223 	u32 coresrencr;
224 	u32 pex2pmrdsr;
225 	u32 ddrc1cr;
226 	u32 ddrc2cr;
227 	u32 ddrc3cr;
228 	u32 ddrc4cr;
229 	u32 ddrgcr;
230 	u32 resv13[120];
231 	u32 qeioclkcr;
232 	u32 etsecmcr;
233 	u32 sdhciovserlcr;
234 	u32 resv14[61];
235 	u32 sparecr[8];
236 };
237 
238 /* Clocking */
239 struct ccsr_clk {
240 	struct {
241 		u32 clkcncsr;	/* core cluster n clock control status */
242 		u8  res_004[0x1c];
243 	} clkcsr[2];
244 	u8	res_040[0x7c0]; /* 0x100 */
245 	struct {
246 		u32 pllcngsr;
247 		u8 res_804[0x1c];
248 	} pllcgsr[2];
249 	u8	res_840[0x1c0];
250 	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
251 	u8	res_a04[0x1fc];
252 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
253 	u8	res_c04[0x1c];
254 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
255 	u8	res_c24[0x3dc];
256 };
257 
258 /* System Counter */
259 struct sctr_regs {
260 	u32 cntcr;
261 	u32 cntsr;
262 	u32 cntcv1;
263 	u32 cntcv2;
264 	u32 resv1[4];
265 	u32 cntfid0;
266 	u32 cntfid1;
267 	u32 resv2[1002];
268 	u32 counterid[12];
269 };
270 
271 #define MAX_SERDES			1
272 #define SRDS_MAX_LANES			4
273 #define SRDS_MAX_BANK			2
274 
275 #define SRDS_RSTCTL_RST			0x80000000
276 #define SRDS_RSTCTL_RSTDONE		0x40000000
277 #define SRDS_RSTCTL_RSTERR		0x20000000
278 #define SRDS_RSTCTL_SWRST		0x10000000
279 #define SRDS_RSTCTL_SDEN		0x00000020
280 #define SRDS_RSTCTL_SDRST_B		0x00000040
281 #define SRDS_RSTCTL_PLLRST_B		0x00000080
282 #define SRDS_PLLCR0_POFF		0x80000000
283 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
284 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
285 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
286 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
287 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
288 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
289 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
290 #define SRDS_PLLCR0_PLL_LCK		0x00800000
291 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
292 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
293 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
294 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
295 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
296 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
297 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
298 #define SRDS_PLLCR1_PLL_BWSEL		0x08000000
299 
300 struct ccsr_serdes {
301 	struct {
302 		u32	rstctl;	/* Reset Control Register */
303 
304 		u32	pllcr0; /* PLL Control Register 0 */
305 
306 		u32	pllcr1; /* PLL Control Register 1 */
307 		u32	res_0c;	/* 0x00c */
308 		u32	pllcr3;
309 		u32	pllcr4;
310 		u8	res_18[0x20-0x18];
311 	} bank[2];
312 	u8	res_40[0x90-0x40];
313 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
314 	u8	res_94[0xa0-0x94];
315 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
316 	u8	res_a4[0xb0-0xa4];
317 	u32	srdsgr0;	/* 0xb0 General Register 0 */
318 	u8	res_b4[0xe0-0xb4];
319 	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
320 	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
321 	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
322 	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
323 	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
324 	u8	res_f4[0x100-0xf4];
325 	struct {
326 		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
327 		u8	res_104[0x120-0x104];
328 	} srdslnpssr[4];
329 	u8	res_180[0x300-0x180];
330 	u32	srdspexeqcr;
331 	u32	srdspexeqpcr[11];
332 	u8	res_330[0x400-0x330];
333 	u32	srdspexapcr;
334 	u8	res_404[0x440-0x404];
335 	u32	srdspexbpcr;
336 	u8	res_444[0x800-0x444];
337 	struct {
338 		u32	gcr0;	/* 0x800 General Control Register 0 */
339 		u32	gcr1;	/* 0x804 General Control Register 1 */
340 		u32	gcr2;	/* 0x808 General Control Register 2 */
341 		u32	sscr0;
342 		u32	recr0;	/* 0x810 Receive Equalization Control */
343 		u32	recr1;
344 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
345 		u32	sscr1;
346 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
347 		u8	res_824[0x83c-0x824];
348 		u32	tcsr3;
349 	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
350 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
351 };
352 
353 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
354 #define CCI400_CTRLORD_EN_BARRIER	0
355 #define CCI400_SHAORD_NON_SHAREABLE	0x00000002
356 #define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
357 #define CCI400_SNOOP_REQ_EN		0x00000001
358 
359 /* CCI-400 registers */
360 struct ccsr_cci400 {
361 	u32 ctrl_ord;			/* Control Override */
362 	u32 spec_ctrl;			/* Speculation Control */
363 	u32 secure_access;		/* Secure Access */
364 	u32 status;			/* Status */
365 	u32 impr_err;			/* Imprecise Error */
366 	u8 res_14[0x100 - 0x14];
367 	u32 pmcr;			/* Performance Monitor Control */
368 	u8 res_104[0xfd0 - 0x104];
369 	u32 pid[8];			/* Peripheral ID */
370 	u32 cid[4];			/* Component ID */
371 	struct {
372 		u32 snoop_ctrl;		/* Snoop Control */
373 		u32 sha_ord;		/* Shareable Override */
374 		u8 res_1008[0x1100 - 0x1008];
375 		u32 rc_qos_ord;		/* read channel QoS Value Override */
376 		u32 wc_qos_ord;		/* read channel QoS Value Override */
377 		u8 res_1108[0x110c - 0x1108];
378 		u32 qos_ctrl;		/* QoS Control */
379 		u32 max_ot;		/* Max OT */
380 		u8 res_1114[0x1130 - 0x1114];
381 		u32 target_lat;		/* Target Latency */
382 		u32 latency_regu;	/* Latency Regulation */
383 		u32 qos_range;		/* QoS Range */
384 		u8 res_113c[0x2000 - 0x113c];
385 	} slave[5];			/* Slave Interface */
386 	u8 res_6000[0x9004 - 0x6000];
387 	u32 cycle_counter;		/* Cycle counter */
388 	u32 count_ctrl;			/* Count Control */
389 	u32 overflow_status;		/* Overflow Flag Status */
390 	u8 res_9010[0xa000 - 0x9010];
391 	struct {
392 		u32 event_select;	/* Event Select */
393 		u32 event_count;	/* Event Count */
394 		u32 counter_ctrl;	/* Counter Control */
395 		u32 overflow_status;	/* Overflow Flag Status */
396 		u8 res_a010[0xb000 - 0xa010];
397 	} pcounter[4];			/* Performance Counter */
398 	u8 res_e004[0x10000 - 0xe004];
399 };
400 
401 /* AHCI (sata) register map */
402 struct ccsr_ahci {
403 	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
404 	u32 pcfg;	/* port config */
405 	u32 ppcfg;	/* port phy1 config */
406 	u32 pp2c;	/* port phy2 config */
407 	u32 pp3c;	/* port phy3 config */
408 	u32 pp4c;	/* port phy4 config */
409 	u32 pp5c;	/* port phy5 config */
410 	u32 paxic;	/* port AXI config */
411 	u32 axicc;	/* AXI cache control */
412 	u32 axipc;	/* AXI PROT control */
413 	u32 ptc;	/* port Trans Config */
414 	u32 pts;	/* port Trans Status */
415 	u32 plc;	/* port link config */
416 	u32 plc1;	/* port link config1 */
417 	u32 plc2;	/* port link config2 */
418 	u32 pls;	/* port link status */
419 	u32 pls1;	/* port link status1 */
420 	u32 pcmdc;	/* port CMD config */
421 	u32 ppcs;	/* port phy control status */
422 	u32 pberr;	/* port 0/1 BIST error */
423 	u32 cmds;	/* port 0/1 CMD status error */
424 };
425 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
426