1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8 #define __ASM_ARCH_LS102XA_IMMAP_H_ 9 #include <fsl_immap.h> 10 11 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 12 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 13 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 14 #define IS_E_PROCESSOR(svr) (svr & 0x80000) 15 #define IS_SVR_REV(svr, maj, min) \ 16 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) 17 18 #define SOC_VER_SLS1020 0x00 19 #define SOC_VER_LS1020 0x10 20 #define SOC_VER_LS1021 0x11 21 #define SOC_VER_LS1022 0x12 22 23 #define SOC_MAJOR_VER_1_0 0x1 24 #define SOC_MAJOR_VER_2_0 0x2 25 26 #define CCSR_BRR_OFFSET 0xe4 27 #define CCSR_SCRATCHRW1_OFFSET 0x200 28 29 #define RCWSR0_SYS_PLL_RAT_SHIFT 25 30 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 31 #define RCWSR0_MEM_PLL_RAT_SHIFT 16 32 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 33 34 #define RCWSR4_SRDS1_PRTCL_SHIFT 24 35 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 36 37 #define TIMER_COMP_VAL 0xffffffffffffffffull 38 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 39 #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 40 41 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 42 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 43 44 #define DCFG_DCSR_PORCR1 0 45 46 /* 47 * Define default values for some CCSR macros to make header files cleaner 48 * 49 * To completely disable CCSR relocation in a board header file, define 50 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 51 * to a value that is the same as CONFIG_SYS_CCSRBAR. 52 */ 53 54 #ifdef CONFIG_SYS_CCSRBAR_PHYS 55 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." 56 #endif 57 58 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 60 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 61 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 62 #endif 63 64 #ifndef CONFIG_SYS_CCSRBAR 65 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR 66 #endif 67 68 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 69 #ifdef CONFIG_PHYS_64BIT 70 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 71 #else 72 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 73 #endif 74 #endif 75 76 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR 78 #endif 79 80 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 81 CONFIG_SYS_CCSRBAR_PHYS_LOW) 82 83 struct sys_info { 84 unsigned long freq_processor[CONFIG_MAX_CPUS]; 85 unsigned long freq_systembus; 86 unsigned long freq_ddrbus; 87 unsigned long freq_localbus; 88 }; 89 90 /* Device Configuration and Pin Control */ 91 struct ccsr_gur { 92 u32 porsr1; /* POR status 1 */ 93 u32 porsr2; /* POR status 2 */ 94 u8 res_008[0x20-0x8]; 95 u32 gpporcr1; /* General-purpose POR configuration */ 96 u32 gpporcr2; 97 u32 dcfg_fusesr; /* Fuse status register */ 98 u8 res_02c[0x70-0x2c]; 99 u32 devdisr; /* Device disable control */ 100 u32 devdisr2; /* Device disable control 2 */ 101 u32 devdisr3; /* Device disable control 3 */ 102 u32 devdisr4; /* Device disable control 4 */ 103 u32 devdisr5; /* Device disable control 5 */ 104 u8 res_084[0x94-0x84]; 105 u32 coredisru; /* uppper portion for support of 64 cores */ 106 u32 coredisrl; /* lower portion for support of 64 cores */ 107 u8 res_09c[0xa4-0x9c]; 108 u32 svr; /* System version */ 109 u8 res_0a8[0xb0-0xa8]; 110 u32 rstcr; /* Reset control */ 111 u32 rstrqpblsr; /* Reset request preboot loader status */ 112 u8 res_0b8[0xc0-0xb8]; 113 u32 rstrqmr1; /* Reset request mask */ 114 u8 res_0c4[0xc8-0xc4]; 115 u32 rstrqsr1; /* Reset request status */ 116 u8 res_0cc[0xd4-0xcc]; 117 u32 rstrqwdtmrl; /* Reset request WDT mask */ 118 u8 res_0d8[0xdc-0xd8]; 119 u32 rstrqwdtsrl; /* Reset request WDT status */ 120 u8 res_0e0[0xe4-0xe0]; 121 u32 brrl; /* Boot release */ 122 u8 res_0e8[0x100-0xe8]; 123 u32 rcwsr[16]; /* Reset control word status */ 124 #define RCW_SB_EN_REG_INDEX 7 125 #define RCW_SB_EN_MASK 0x00200000 126 u8 res_140[0x200-0x140]; 127 u32 scratchrw[4]; /* Scratch Read/Write */ 128 u8 res_210[0x300-0x210]; 129 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 130 u8 res_310[0x400-0x310]; 131 u32 crstsr; 132 u8 res_404[0x550-0x404]; 133 u32 sataliodnr; 134 u8 res_554[0x604-0x554]; 135 u32 pamubypenr; 136 u32 dmacr1; 137 u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 138 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 139 struct { 140 u32 upper; 141 u32 lower; 142 } tp_cluster[1]; /* Core Cluster n Topology Register */ 143 u8 res_848[0xe60-0x848]; 144 u32 ddrclkdr; 145 u8 res_e60[0xe68-0xe64]; 146 u32 ifcclkdr; 147 u8 res_e68[0xe80-0xe6c]; 148 u32 sdhcpcr; 149 }; 150 151 #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 152 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 153 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 154 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 155 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 156 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 157 #define SCFG_QSPI_CLKSEL 0xc0100000 158 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 159 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 160 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 161 #define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 162 #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 163 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 164 #define SCFG_ENDIANCR_LE 0x80000000 165 #define SCFG_DPSLPCR_WDRR_EN 0x00000001 166 #define SCFG_PMCINTECR_LPUART 0x40000000 167 #define SCFG_PMCINTECR_FTM 0x20000000 168 #define SCFG_PMCINTECR_GPIO 0x10000000 169 #define SCFG_PMCINTECR_IRQ0 0x08000000 170 #define SCFG_PMCINTECR_IRQ1 0x04000000 171 #define SCFG_PMCINTECR_ETSECRXG0 0x00800000 172 #define SCFG_PMCINTECR_ETSECRXG1 0x00400000 173 #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 174 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 175 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 176 177 #define SCFG_BASE 0x01570000 178 #define SCFG_USB3PRM1CR 0x070 179 #define SCFG_USB_TXVREFTUNE 0x9 180 #define SCFG_USB_SQRXTUNE_MASK 0x7 181 #define SCFG_USB3PRM2CR 0x074 182 #define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00 183 #define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00 184 185 #define USB_PHY_BASE 0x08510000 186 #define USB_PHY_RX_OVRD_IN_HI 0x200c 187 #define USB_PHY_RX_EQ_VAL_1 0x0000 188 #define USB_PHY_RX_EQ_VAL_2 0x8000 189 #define USB_PHY_RX_EQ_VAL_3 0x8004 190 #define USB_PHY_RX_EQ_VAL_4 0x800C 191 192 /* Supplemental Configuration Unit */ 193 struct ccsr_scfg { 194 u32 dpslpcr; 195 u32 resv0[2]; 196 u32 etsecclkdpslpcr; 197 u32 resv1[5]; 198 u32 fuseovrdcr; 199 u32 pixclkcr; 200 u32 resv2[5]; 201 u32 spimsicr; 202 u32 resv3[6]; 203 u32 pex1pmwrcr; 204 u32 pex1pmrdsr; 205 u32 resv4[3]; 206 u32 usb3prm1cr; 207 u32 usb4prm2cr; 208 u32 pex1rdmsgpldlsbsr; 209 u32 pex1rdmsgpldmsbsr; 210 u32 pex2rdmsgpldlsbsr; 211 u32 pex2rdmsgpldmsbsr; 212 u32 pex1rdmmsgrqsr; 213 u32 pex2rdmmsgrqsr; 214 u32 spimsiclrcr; 215 u32 pexmscportsr[2]; 216 u32 pex2pmwrcr; 217 u32 resv5[24]; 218 u32 mac1_streamid; 219 u32 mac2_streamid; 220 u32 mac3_streamid; 221 u32 pex1_streamid; 222 u32 pex2_streamid; 223 u32 dma_streamid; 224 u32 sata_streamid; 225 u32 usb3_streamid; 226 u32 qe_streamid; 227 u32 sdhc_streamid; 228 u32 adma_streamid; 229 u32 letechsftrstcr; 230 u32 core0_sft_rst; 231 u32 core1_sft_rst; 232 u32 resv6[1]; 233 u32 usb_hi_addr; 234 u32 etsecclkadjcr; 235 u32 sai_clk; 236 u32 resv7[1]; 237 u32 dcu_streamid; 238 u32 usb2_streamid; 239 u32 ftm_reset; 240 u32 altcbar; 241 u32 qspi_cfg; 242 u32 pmcintecr; 243 u32 pmcintlecr; 244 u32 pmcintsr; 245 u32 qos1; 246 u32 qos2; 247 u32 qos3; 248 u32 cci_cfg; 249 u32 endiancr; 250 u32 etsecdmamcr; 251 u32 usb3prm3cr; 252 u32 resv9[1]; 253 u32 debug_streamid; 254 u32 resv10[5]; 255 u32 snpcnfgcr; 256 u32 hrstcr; 257 u32 intpcr; 258 u32 resv12[20]; 259 u32 scfgrevcr; 260 u32 coresrencr; 261 u32 pex2pmrdsr; 262 u32 eddrtqcfg; 263 u32 ddrc2cr; 264 u32 ddrc3cr; 265 u32 ddrc4cr; 266 u32 ddrgcr; 267 u32 resv13[120]; 268 u32 qeioclkcr; 269 u32 etsecmcr; 270 u32 sdhciovserlcr; 271 u32 resv14[61]; 272 u32 sparecr[8]; 273 u32 resv15[248]; 274 u32 core0sftrstsr; 275 u32 clusterpmcr; 276 }; 277 278 /* Clocking */ 279 struct ccsr_clk { 280 struct { 281 u32 clkcncsr; /* core cluster n clock control status */ 282 u8 res_004[0x1c]; 283 } clkcsr[2]; 284 u8 res_040[0x7c0]; /* 0x100 */ 285 struct { 286 u32 pllcngsr; 287 u8 res_804[0x1c]; 288 } pllcgsr[2]; 289 u8 res_840[0x1c0]; 290 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 291 u8 res_a04[0x1fc]; 292 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 293 u8 res_c04[0x1c]; 294 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 295 u8 res_c24[0x3dc]; 296 }; 297 298 /* System Counter */ 299 struct sctr_regs { 300 u32 cntcr; 301 u32 cntsr; 302 u32 cntcv1; 303 u32 cntcv2; 304 u32 resv1[4]; 305 u32 cntfid0; 306 u32 cntfid1; 307 u32 resv2[1002]; 308 u32 counterid[12]; 309 }; 310 311 #define MAX_SERDES 1 312 #define SRDS_MAX_LANES 4 313 #define SRDS_MAX_BANK 2 314 315 #define SRDS_RSTCTL_RST 0x80000000 316 #define SRDS_RSTCTL_RSTDONE 0x40000000 317 #define SRDS_RSTCTL_RSTERR 0x20000000 318 #define SRDS_RSTCTL_SWRST 0x10000000 319 #define SRDS_RSTCTL_SDEN 0x00000020 320 #define SRDS_RSTCTL_SDRST_B 0x00000040 321 #define SRDS_RSTCTL_PLLRST_B 0x00000080 322 #define SRDS_PLLCR0_POFF 0x80000000 323 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 324 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 325 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 326 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 327 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 328 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 329 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 330 #define SRDS_PLLCR0_PLL_LCK 0x00800000 331 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 332 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 333 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 334 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 335 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 336 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 337 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 338 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 339 340 struct ccsr_serdes { 341 struct { 342 u32 rstctl; /* Reset Control Register */ 343 344 u32 pllcr0; /* PLL Control Register 0 */ 345 346 u32 pllcr1; /* PLL Control Register 1 */ 347 u32 res_0c; /* 0x00c */ 348 u32 pllcr3; 349 u32 pllcr4; 350 u8 res_18[0x20-0x18]; 351 } bank[2]; 352 u8 res_40[0x90-0x40]; 353 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 354 u8 res_94[0xa0-0x94]; 355 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 356 u8 res_a4[0xb0-0xa4]; 357 u32 srdsgr0; /* 0xb0 General Register 0 */ 358 u8 res_b4[0xe0-0xb4]; 359 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 360 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 361 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 362 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 363 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 364 u8 res_f4[0x100-0xf4]; 365 struct { 366 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 367 u8 res_104[0x120-0x104]; 368 } srdslnpssr[4]; 369 u8 res_180[0x300-0x180]; 370 u32 srdspexeqcr; 371 u32 srdspexeqpcr[11]; 372 u8 res_330[0x400-0x330]; 373 u32 srdspexapcr; 374 u8 res_404[0x440-0x404]; 375 u32 srdspexbpcr; 376 u8 res_444[0x800-0x444]; 377 struct { 378 u32 gcr0; /* 0x800 General Control Register 0 */ 379 u32 gcr1; /* 0x804 General Control Register 1 */ 380 u32 gcr2; /* 0x808 General Control Register 2 */ 381 u32 sscr0; 382 u32 recr0; /* 0x810 Receive Equalization Control */ 383 u32 recr1; 384 u32 tecr0; /* 0x818 Transmit Equalization Control */ 385 u32 sscr1; 386 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 387 u8 res_824[0x83c-0x824]; 388 u32 tcsr3; 389 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 390 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 391 }; 392 393 394 395 /* AHCI (sata) register map */ 396 struct ccsr_ahci { 397 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 398 u32 pcfg; /* port config */ 399 u32 ppcfg; /* port phy1 config */ 400 u32 pp2c; /* port phy2 config */ 401 u32 pp3c; /* port phy3 config */ 402 u32 pp4c; /* port phy4 config */ 403 u32 pp5c; /* port phy5 config */ 404 u32 paxic; /* port AXI config */ 405 u32 axicc; /* AXI cache control */ 406 u32 axipc; /* AXI PROT control */ 407 u32 ptc; /* port Trans Config */ 408 u32 pts; /* port Trans Status */ 409 u32 plc; /* port link config */ 410 u32 plc1; /* port link config1 */ 411 u32 plc2; /* port link config2 */ 412 u32 pls; /* port link status */ 413 u32 pls1; /* port link status1 */ 414 u32 pcmdc; /* port CMD config */ 415 u32 ppcs; /* port phy control status */ 416 u32 pberr; /* port 0/1 BIST error */ 417 u32 cmds; /* port 0/1 CMD status error */ 418 }; 419 420 #define RCPM_POWMGTCSR 0x130 421 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 422 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 423 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 424 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 425 #define RCPM_IPPDEXPCR0 0x140 426 #define RCPM_IPPDEXPCR0_ETSEC 0x80000000 427 #define RCPM_IPPDEXPCR0_GPIO 0x00000040 428 #define RCPM_IPPDEXPCR1 0x144 429 #define RCPM_IPPDEXPCR1_LPUART 0x40000000 430 #define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 431 #define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 432 #define RCPM_NFIQOUTR 0x15c 433 #define RCPM_NIRQOUTR 0x16c 434 #define RCPM_DSIMSKR 0x18c 435 #define RCPM_CLPCL10SETR 0x1c4 436 #define RCPM_CLPCL10SETR_C0 0x00000001 437 438 struct ccsr_rcpm { 439 u8 rev1[0x4c]; 440 u32 twaitsr; 441 u8 rev2[0xe0]; 442 u32 powmgtcsr; 443 u8 rev3[0xc]; 444 u32 ippdexpcr0; 445 u32 ippdexpcr1; 446 u8 rev4[0x14]; 447 u32 nfiqoutr; 448 u8 rev5[0xc]; 449 u32 nirqoutr; 450 u8 rev6[0x1c]; 451 u32 dsimskr; 452 u8 rev7[0x34]; 453 u32 clpcl10setr; 454 }; 455 456 uint get_svr(void); 457 458 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 459