1d60a2099SWang Huan /* 2d60a2099SWang Huan * Copyright 2014 Freescale Semiconductor, Inc. 3d60a2099SWang Huan * 4d60a2099SWang Huan * SPDX-License-Identifier: GPL-2.0+ 5d60a2099SWang Huan */ 6d60a2099SWang Huan 7d60a2099SWang Huan #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8d60a2099SWang Huan #define __ASM_ARCH_LS102XA_IMMAP_H_ 963b2316cSAshish Kumar #include <fsl_immap.h> 10d60a2099SWang Huan 11d60a2099SWang Huan #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 12d60a2099SWang Huan #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 13d60a2099SWang Huan #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 14d60a2099SWang Huan #define IS_E_PROCESSOR(svr) (svr & 0x80000) 150c028a03SShengzhou Liu #define IS_SVR_REV(svr, maj, min) \ 160c028a03SShengzhou Liu ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) 17d60a2099SWang Huan 18d60a2099SWang Huan #define SOC_VER_SLS1020 0x00 19d60a2099SWang Huan #define SOC_VER_LS1020 0x10 20d60a2099SWang Huan #define SOC_VER_LS1021 0x11 21d60a2099SWang Huan #define SOC_VER_LS1022 0x12 22d60a2099SWang Huan 23036f3f33SAlison Wang #define SOC_MAJOR_VER_1_0 0x1 24036f3f33SAlison Wang #define SOC_MAJOR_VER_2_0 0x2 25036f3f33SAlison Wang 261a2826f6SXiubo Li #define CCSR_BRR_OFFSET 0xe4 271a2826f6SXiubo Li #define CCSR_SCRATCHRW1_OFFSET 0x200 281a2826f6SXiubo Li 29d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_SHIFT 25 30d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 31d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_SHIFT 16 32d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 33d60a2099SWang Huan 34d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_SHIFT 24 35d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 36d60a2099SWang Huan 372b714cfaSAlison Wang #define TIMER_COMP_VAL 0xffffffffffffffffull 38d60a2099SWang Huan #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 39d60a2099SWang Huan #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 40d60a2099SWang Huan 418ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 428ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 438ab967b6SAlison Wang 448ab967b6SAlison Wang #define DCFG_DCSR_PORCR1 0 458ab967b6SAlison Wang 4660d51736SAlison Wang /* 4760d51736SAlison Wang * Define default values for some CCSR macros to make header files cleaner 4860d51736SAlison Wang * 4960d51736SAlison Wang * To completely disable CCSR relocation in a board header file, define 5060d51736SAlison Wang * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 5160d51736SAlison Wang * to a value that is the same as CONFIG_SYS_CCSRBAR. 5260d51736SAlison Wang */ 5360d51736SAlison Wang 5460d51736SAlison Wang #ifdef CONFIG_SYS_CCSRBAR_PHYS 5560d51736SAlison Wang #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." 5660d51736SAlison Wang #endif 5760d51736SAlison Wang 5860d51736SAlison Wang #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 5960d51736SAlison Wang #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 6060d51736SAlison Wang #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 6160d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 6260d51736SAlison Wang #endif 6360d51736SAlison Wang 6460d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR 6560d51736SAlison Wang #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR 6660d51736SAlison Wang #endif 6760d51736SAlison Wang 6860d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 6960d51736SAlison Wang #ifdef CONFIG_PHYS_64BIT 7060d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 7160d51736SAlison Wang #else 7260d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 7360d51736SAlison Wang #endif 7460d51736SAlison Wang #endif 7560d51736SAlison Wang 7660d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 7760d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR 7860d51736SAlison Wang #endif 7960d51736SAlison Wang 8060d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 8160d51736SAlison Wang CONFIG_SYS_CCSRBAR_PHYS_LOW) 8260d51736SAlison Wang 83d60a2099SWang Huan struct sys_info { 84d60a2099SWang Huan unsigned long freq_processor[CONFIG_MAX_CPUS]; 85d60a2099SWang Huan unsigned long freq_systembus; 86d60a2099SWang Huan unsigned long freq_ddrbus; 87d60a2099SWang Huan unsigned long freq_localbus; 88d60a2099SWang Huan }; 89d60a2099SWang Huan 90d60a2099SWang Huan /* Device Configuration and Pin Control */ 91d60a2099SWang Huan struct ccsr_gur { 92d60a2099SWang Huan u32 porsr1; /* POR status 1 */ 93d60a2099SWang Huan u32 porsr2; /* POR status 2 */ 94d60a2099SWang Huan u8 res_008[0x20-0x8]; 95d60a2099SWang Huan u32 gpporcr1; /* General-purpose POR configuration */ 96d60a2099SWang Huan u32 gpporcr2; 97d60a2099SWang Huan u32 dcfg_fusesr; /* Fuse status register */ 98d60a2099SWang Huan u8 res_02c[0x70-0x2c]; 99d60a2099SWang Huan u32 devdisr; /* Device disable control */ 100d60a2099SWang Huan u32 devdisr2; /* Device disable control 2 */ 101d60a2099SWang Huan u32 devdisr3; /* Device disable control 3 */ 102d60a2099SWang Huan u32 devdisr4; /* Device disable control 4 */ 103d60a2099SWang Huan u32 devdisr5; /* Device disable control 5 */ 104d60a2099SWang Huan u8 res_084[0x94-0x84]; 105d60a2099SWang Huan u32 coredisru; /* uppper portion for support of 64 cores */ 106d60a2099SWang Huan u32 coredisrl; /* lower portion for support of 64 cores */ 107d60a2099SWang Huan u8 res_09c[0xa4-0x9c]; 108d60a2099SWang Huan u32 svr; /* System version */ 109d60a2099SWang Huan u8 res_0a8[0xb0-0xa8]; 110d60a2099SWang Huan u32 rstcr; /* Reset control */ 111d60a2099SWang Huan u32 rstrqpblsr; /* Reset request preboot loader status */ 112d60a2099SWang Huan u8 res_0b8[0xc0-0xb8]; 113d60a2099SWang Huan u32 rstrqmr1; /* Reset request mask */ 114d60a2099SWang Huan u8 res_0c4[0xc8-0xc4]; 115d60a2099SWang Huan u32 rstrqsr1; /* Reset request status */ 116d60a2099SWang Huan u8 res_0cc[0xd4-0xcc]; 117d60a2099SWang Huan u32 rstrqwdtmrl; /* Reset request WDT mask */ 118d60a2099SWang Huan u8 res_0d8[0xdc-0xd8]; 119d60a2099SWang Huan u32 rstrqwdtsrl; /* Reset request WDT status */ 120d60a2099SWang Huan u8 res_0e0[0xe4-0xe0]; 121d60a2099SWang Huan u32 brrl; /* Boot release */ 122d60a2099SWang Huan u8 res_0e8[0x100-0xe8]; 123d60a2099SWang Huan u32 rcwsr[16]; /* Reset control word status */ 1240a6b2714SAneesh Bansal #define RCW_SB_EN_REG_INDEX 7 1250a6b2714SAneesh Bansal #define RCW_SB_EN_MASK 0x00200000 126d60a2099SWang Huan u8 res_140[0x200-0x140]; 127d60a2099SWang Huan u32 scratchrw[4]; /* Scratch Read/Write */ 128d60a2099SWang Huan u8 res_210[0x300-0x210]; 129d60a2099SWang Huan u32 scratchw1r[4]; /* Scratch Read (Write once) */ 130d60a2099SWang Huan u8 res_310[0x400-0x310]; 131d60a2099SWang Huan u32 crstsr; 132d60a2099SWang Huan u8 res_404[0x550-0x404]; 133d60a2099SWang Huan u32 sataliodnr; 134d60a2099SWang Huan u8 res_554[0x604-0x554]; 135d60a2099SWang Huan u32 pamubypenr; 136d60a2099SWang Huan u32 dmacr1; 137d60a2099SWang Huan u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 138d60a2099SWang Huan u32 tp_ityp[64]; /* Topology Initiator Type Register */ 139d60a2099SWang Huan struct { 140d60a2099SWang Huan u32 upper; 141d60a2099SWang Huan u32 lower; 142d60a2099SWang Huan } tp_cluster[1]; /* Core Cluster n Topology Register */ 143d60a2099SWang Huan u8 res_848[0xe60-0x848]; 144d60a2099SWang Huan u32 ddrclkdr; 145d60a2099SWang Huan u8 res_e60[0xe68-0xe64]; 146d60a2099SWang Huan u32 ifcclkdr; 147d60a2099SWang Huan u8 res_e68[0xe80-0xe6c]; 148d60a2099SWang Huan u32 sdhcpcr; 149d60a2099SWang Huan }; 150d60a2099SWang Huan 151ebe4c1e6SClaudiu Manoil #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 1525757e06cShoria.geanta@freescale.com #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 153d60a2099SWang Huan #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 1540f5e5579SAlison Wang #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 1550f5e5579SAlison Wang #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 156d60a2099SWang Huan #define SCFG_PIXCLKCR_PXCKEN 0x80000000 157d612f0abSAlison Wang #define SCFG_QSPI_CLKSEL 0xc0100000 158762b3535SYao Yuan #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 159762b3535SYao Yuan #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 160762b3535SYao Yuan #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 161762b3535SYao Yuan #define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000 162762b3535SYao Yuan #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000 163762b3535SYao Yuan #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000 16488c857dfSAlison Wang #define SCFG_ENDIANCR_LE 0x80000000 165349cfc97SHongbo Zhang #define SCFG_DPSLPCR_WDRR_EN 0x00000001 166349cfc97SHongbo Zhang #define SCFG_PMCINTECR_LPUART 0x40000000 167349cfc97SHongbo Zhang #define SCFG_PMCINTECR_FTM 0x20000000 168349cfc97SHongbo Zhang #define SCFG_PMCINTECR_GPIO 0x10000000 169349cfc97SHongbo Zhang #define SCFG_PMCINTECR_IRQ0 0x08000000 170349cfc97SHongbo Zhang #define SCFG_PMCINTECR_IRQ1 0x04000000 171349cfc97SHongbo Zhang #define SCFG_PMCINTECR_ETSECRXG0 0x00800000 172349cfc97SHongbo Zhang #define SCFG_PMCINTECR_ETSECRXG1 0x00400000 173349cfc97SHongbo Zhang #define SCFG_PMCINTECR_ETSECERRG0 0x00080000 174349cfc97SHongbo Zhang #define SCFG_PMCINTECR_ETSECERRG1 0x00040000 175349cfc97SHongbo Zhang #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000 176d60a2099SWang Huan 177*83fa7118SRan Wang #define SCFG_BASE 0x01570000 178*83fa7118SRan Wang #define SCFG_USB3PRM1CR 0x070 179*83fa7118SRan Wang #define SCFG_USB_TXVREFTUNE 0x9 180*83fa7118SRan Wang 181d60a2099SWang Huan /* Supplemental Configuration Unit */ 182d60a2099SWang Huan struct ccsr_scfg { 183d60a2099SWang Huan u32 dpslpcr; 184d60a2099SWang Huan u32 resv0[2]; 185d60a2099SWang Huan u32 etsecclkdpslpcr; 186d60a2099SWang Huan u32 resv1[5]; 187d60a2099SWang Huan u32 fuseovrdcr; 188d60a2099SWang Huan u32 pixclkcr; 189d60a2099SWang Huan u32 resv2[5]; 190d60a2099SWang Huan u32 spimsicr; 191d60a2099SWang Huan u32 resv3[6]; 192d60a2099SWang Huan u32 pex1pmwrcr; 193d60a2099SWang Huan u32 pex1pmrdsr; 194d60a2099SWang Huan u32 resv4[3]; 195d60a2099SWang Huan u32 usb3prm1cr; 196d60a2099SWang Huan u32 usb4prm2cr; 197d60a2099SWang Huan u32 pex1rdmsgpldlsbsr; 198d60a2099SWang Huan u32 pex1rdmsgpldmsbsr; 199d60a2099SWang Huan u32 pex2rdmsgpldlsbsr; 200d60a2099SWang Huan u32 pex2rdmsgpldmsbsr; 201d60a2099SWang Huan u32 pex1rdmmsgrqsr; 202d60a2099SWang Huan u32 pex2rdmmsgrqsr; 203d60a2099SWang Huan u32 spimsiclrcr; 204ec245fd7SMinghuan Lian u32 pexmscportsr[2]; 205d60a2099SWang Huan u32 pex2pmwrcr; 206d60a2099SWang Huan u32 resv5[24]; 207d60a2099SWang Huan u32 mac1_streamid; 208d60a2099SWang Huan u32 mac2_streamid; 209d60a2099SWang Huan u32 mac3_streamid; 210d60a2099SWang Huan u32 pex1_streamid; 211d60a2099SWang Huan u32 pex2_streamid; 212d60a2099SWang Huan u32 dma_streamid; 213d60a2099SWang Huan u32 sata_streamid; 214d60a2099SWang Huan u32 usb3_streamid; 215d60a2099SWang Huan u32 qe_streamid; 216d60a2099SWang Huan u32 sdhc_streamid; 217d60a2099SWang Huan u32 adma_streamid; 218d60a2099SWang Huan u32 letechsftrstcr; 219d60a2099SWang Huan u32 core0_sft_rst; 220d60a2099SWang Huan u32 core1_sft_rst; 221d60a2099SWang Huan u32 resv6[1]; 222d60a2099SWang Huan u32 usb_hi_addr; 223d60a2099SWang Huan u32 etsecclkadjcr; 224d60a2099SWang Huan u32 sai_clk; 225d60a2099SWang Huan u32 resv7[1]; 226d60a2099SWang Huan u32 dcu_streamid; 227d60a2099SWang Huan u32 usb2_streamid; 228d60a2099SWang Huan u32 ftm_reset; 229d60a2099SWang Huan u32 altcbar; 230d60a2099SWang Huan u32 qspi_cfg; 231d60a2099SWang Huan u32 pmcintecr; 232d60a2099SWang Huan u32 pmcintlecr; 233d60a2099SWang Huan u32 pmcintsr; 234d60a2099SWang Huan u32 qos1; 235d60a2099SWang Huan u32 qos2; 236d60a2099SWang Huan u32 qos3; 237d60a2099SWang Huan u32 cci_cfg; 23888c857dfSAlison Wang u32 endiancr; 239d60a2099SWang Huan u32 etsecdmamcr; 240d60a2099SWang Huan u32 usb3prm3cr; 241d60a2099SWang Huan u32 resv9[1]; 242d60a2099SWang Huan u32 debug_streamid; 243d60a2099SWang Huan u32 resv10[5]; 244d60a2099SWang Huan u32 snpcnfgcr; 245349cfc97SHongbo Zhang u32 hrstcr; 246d60a2099SWang Huan u32 intpcr; 247d60a2099SWang Huan u32 resv12[20]; 248d60a2099SWang Huan u32 scfgrevcr; 249d60a2099SWang Huan u32 coresrencr; 250d60a2099SWang Huan u32 pex2pmrdsr; 2516c4a1ebaSYao Yuan u32 eddrtqcfg; 252d60a2099SWang Huan u32 ddrc2cr; 253d60a2099SWang Huan u32 ddrc3cr; 254d60a2099SWang Huan u32 ddrc4cr; 255d60a2099SWang Huan u32 ddrgcr; 256d60a2099SWang Huan u32 resv13[120]; 257d60a2099SWang Huan u32 qeioclkcr; 258d60a2099SWang Huan u32 etsecmcr; 259d60a2099SWang Huan u32 sdhciovserlcr; 260d60a2099SWang Huan u32 resv14[61]; 261d8222dbeSTang Yuantian u32 sparecr[8]; 262349cfc97SHongbo Zhang u32 resv15[248]; 263349cfc97SHongbo Zhang u32 core0sftrstsr; 264349cfc97SHongbo Zhang u32 clusterpmcr; 265d60a2099SWang Huan }; 266d60a2099SWang Huan 267d60a2099SWang Huan /* Clocking */ 268d60a2099SWang Huan struct ccsr_clk { 269d60a2099SWang Huan struct { 270d60a2099SWang Huan u32 clkcncsr; /* core cluster n clock control status */ 271d60a2099SWang Huan u8 res_004[0x1c]; 272d60a2099SWang Huan } clkcsr[2]; 273d60a2099SWang Huan u8 res_040[0x7c0]; /* 0x100 */ 274d60a2099SWang Huan struct { 275d60a2099SWang Huan u32 pllcngsr; 276d60a2099SWang Huan u8 res_804[0x1c]; 277d60a2099SWang Huan } pllcgsr[2]; 278d60a2099SWang Huan u8 res_840[0x1c0]; 279d60a2099SWang Huan u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 280d60a2099SWang Huan u8 res_a04[0x1fc]; 281d60a2099SWang Huan u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 282d60a2099SWang Huan u8 res_c04[0x1c]; 283d60a2099SWang Huan u32 plldgsr; /* 0xc20 DDR PLL General Status */ 284d60a2099SWang Huan u8 res_c24[0x3dc]; 285d60a2099SWang Huan }; 286d60a2099SWang Huan 287d60a2099SWang Huan /* System Counter */ 288d60a2099SWang Huan struct sctr_regs { 289d60a2099SWang Huan u32 cntcr; 290d60a2099SWang Huan u32 cntsr; 291d60a2099SWang Huan u32 cntcv1; 292d60a2099SWang Huan u32 cntcv2; 293d60a2099SWang Huan u32 resv1[4]; 294d60a2099SWang Huan u32 cntfid0; 295d60a2099SWang Huan u32 cntfid1; 296d60a2099SWang Huan u32 resv2[1002]; 297d60a2099SWang Huan u32 counterid[12]; 298d60a2099SWang Huan }; 299d60a2099SWang Huan 300d60a2099SWang Huan #define MAX_SERDES 1 301d60a2099SWang Huan #define SRDS_MAX_LANES 4 302d60a2099SWang Huan #define SRDS_MAX_BANK 2 303d60a2099SWang Huan 304d60a2099SWang Huan #define SRDS_RSTCTL_RST 0x80000000 305d60a2099SWang Huan #define SRDS_RSTCTL_RSTDONE 0x40000000 306d60a2099SWang Huan #define SRDS_RSTCTL_RSTERR 0x20000000 307d60a2099SWang Huan #define SRDS_RSTCTL_SWRST 0x10000000 308d60a2099SWang Huan #define SRDS_RSTCTL_SDEN 0x00000020 309d60a2099SWang Huan #define SRDS_RSTCTL_SDRST_B 0x00000040 310d60a2099SWang Huan #define SRDS_RSTCTL_PLLRST_B 0x00000080 311d60a2099SWang Huan #define SRDS_PLLCR0_POFF 0x80000000 312d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 313d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 314d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 315d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 316d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 317d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 318d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 319d60a2099SWang Huan #define SRDS_PLLCR0_PLL_LCK 0x00800000 320d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 321d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 322d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 323d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 324d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 325d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 326d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 327d60a2099SWang Huan #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 328d60a2099SWang Huan 329d60a2099SWang Huan struct ccsr_serdes { 330d60a2099SWang Huan struct { 331d60a2099SWang Huan u32 rstctl; /* Reset Control Register */ 332d60a2099SWang Huan 333d60a2099SWang Huan u32 pllcr0; /* PLL Control Register 0 */ 334d60a2099SWang Huan 335d60a2099SWang Huan u32 pllcr1; /* PLL Control Register 1 */ 336d60a2099SWang Huan u32 res_0c; /* 0x00c */ 337d60a2099SWang Huan u32 pllcr3; 338d60a2099SWang Huan u32 pllcr4; 339d60a2099SWang Huan u8 res_18[0x20-0x18]; 340d60a2099SWang Huan } bank[2]; 341d60a2099SWang Huan u8 res_40[0x90-0x40]; 342d60a2099SWang Huan u32 srdstcalcr; /* 0x90 TX Calibration Control */ 343d60a2099SWang Huan u8 res_94[0xa0-0x94]; 344d60a2099SWang Huan u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 345d60a2099SWang Huan u8 res_a4[0xb0-0xa4]; 346d60a2099SWang Huan u32 srdsgr0; /* 0xb0 General Register 0 */ 347d60a2099SWang Huan u8 res_b4[0xe0-0xb4]; 348d60a2099SWang Huan u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 349d60a2099SWang Huan u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 350d60a2099SWang Huan u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 351d60a2099SWang Huan u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 352d60a2099SWang Huan u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 353d60a2099SWang Huan u8 res_f4[0x100-0xf4]; 354d60a2099SWang Huan struct { 355d60a2099SWang Huan u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 356d60a2099SWang Huan u8 res_104[0x120-0x104]; 357d60a2099SWang Huan } srdslnpssr[4]; 358d60a2099SWang Huan u8 res_180[0x300-0x180]; 359d60a2099SWang Huan u32 srdspexeqcr; 360d60a2099SWang Huan u32 srdspexeqpcr[11]; 361d60a2099SWang Huan u8 res_330[0x400-0x330]; 362d60a2099SWang Huan u32 srdspexapcr; 363d60a2099SWang Huan u8 res_404[0x440-0x404]; 364d60a2099SWang Huan u32 srdspexbpcr; 365d60a2099SWang Huan u8 res_444[0x800-0x444]; 366d60a2099SWang Huan struct { 367d60a2099SWang Huan u32 gcr0; /* 0x800 General Control Register 0 */ 368d60a2099SWang Huan u32 gcr1; /* 0x804 General Control Register 1 */ 369d60a2099SWang Huan u32 gcr2; /* 0x808 General Control Register 2 */ 370d60a2099SWang Huan u32 sscr0; 371d60a2099SWang Huan u32 recr0; /* 0x810 Receive Equalization Control */ 372d60a2099SWang Huan u32 recr1; 373d60a2099SWang Huan u32 tecr0; /* 0x818 Transmit Equalization Control */ 374d60a2099SWang Huan u32 sscr1; 375d60a2099SWang Huan u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 376d60a2099SWang Huan u8 res_824[0x83c-0x824]; 377d60a2099SWang Huan u32 tcsr3; 378d60a2099SWang Huan } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 379d60a2099SWang Huan u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 380d60a2099SWang Huan }; 381d60a2099SWang Huan 382d60a2099SWang Huan 383d09e401bSRamneek Mehresh 3844632ad77Stang yuantian /* AHCI (sata) register map */ 3854632ad77Stang yuantian struct ccsr_ahci { 3864632ad77Stang yuantian u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 3874632ad77Stang yuantian u32 pcfg; /* port config */ 3884632ad77Stang yuantian u32 ppcfg; /* port phy1 config */ 3894632ad77Stang yuantian u32 pp2c; /* port phy2 config */ 3904632ad77Stang yuantian u32 pp3c; /* port phy3 config */ 3914632ad77Stang yuantian u32 pp4c; /* port phy4 config */ 3924632ad77Stang yuantian u32 pp5c; /* port phy5 config */ 3934632ad77Stang yuantian u32 paxic; /* port AXI config */ 3944632ad77Stang yuantian u32 axicc; /* AXI cache control */ 3954632ad77Stang yuantian u32 axipc; /* AXI PROT control */ 3964632ad77Stang yuantian u32 ptc; /* port Trans Config */ 3974632ad77Stang yuantian u32 pts; /* port Trans Status */ 3984632ad77Stang yuantian u32 plc; /* port link config */ 3994632ad77Stang yuantian u32 plc1; /* port link config1 */ 4004632ad77Stang yuantian u32 plc2; /* port link config2 */ 4014632ad77Stang yuantian u32 pls; /* port link status */ 4024632ad77Stang yuantian u32 pls1; /* port link status1 */ 4034632ad77Stang yuantian u32 pcmdc; /* port CMD config */ 4044632ad77Stang yuantian u32 ppcs; /* port phy control status */ 4054632ad77Stang yuantian u32 pberr; /* port 0/1 BIST error */ 4064632ad77Stang yuantian u32 cmds; /* port 0/1 CMD status error */ 4074632ad77Stang yuantian }; 4080c028a03SShengzhou Liu 409349cfc97SHongbo Zhang #define RCPM_POWMGTCSR 0x130 410349cfc97SHongbo Zhang #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 411349cfc97SHongbo Zhang #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 412349cfc97SHongbo Zhang #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 413349cfc97SHongbo Zhang #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 414349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR0 0x140 415349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR0_ETSEC 0x80000000 416349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR0_GPIO 0x00000040 417349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR1 0x144 418349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR1_LPUART 0x40000000 419349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000 420349cfc97SHongbo Zhang #define RCPM_IPPDEXPCR1_OCRAM1 0x10000000 421349cfc97SHongbo Zhang #define RCPM_NFIQOUTR 0x15c 422349cfc97SHongbo Zhang #define RCPM_NIRQOUTR 0x16c 423349cfc97SHongbo Zhang #define RCPM_DSIMSKR 0x18c 424349cfc97SHongbo Zhang #define RCPM_CLPCL10SETR 0x1c4 425349cfc97SHongbo Zhang #define RCPM_CLPCL10SETR_C0 0x00000001 426349cfc97SHongbo Zhang 427349cfc97SHongbo Zhang struct ccsr_rcpm { 428349cfc97SHongbo Zhang u8 rev1[0x4c]; 429349cfc97SHongbo Zhang u32 twaitsr; 430349cfc97SHongbo Zhang u8 rev2[0xe0]; 431349cfc97SHongbo Zhang u32 powmgtcsr; 432349cfc97SHongbo Zhang u8 rev3[0xc]; 433349cfc97SHongbo Zhang u32 ippdexpcr0; 434349cfc97SHongbo Zhang u32 ippdexpcr1; 435349cfc97SHongbo Zhang u8 rev4[0x14]; 436349cfc97SHongbo Zhang u32 nfiqoutr; 437349cfc97SHongbo Zhang u8 rev5[0xc]; 438349cfc97SHongbo Zhang u32 nirqoutr; 439349cfc97SHongbo Zhang u8 rev6[0x1c]; 440349cfc97SHongbo Zhang u32 dsimskr; 441349cfc97SHongbo Zhang u8 rev7[0x34]; 442349cfc97SHongbo Zhang u32 clpcl10setr; 443349cfc97SHongbo Zhang }; 444349cfc97SHongbo Zhang 4450c028a03SShengzhou Liu uint get_svr(void); 4460c028a03SShengzhou Liu 447d60a2099SWang Huan #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 448