1d60a2099SWang Huan /* 2d60a2099SWang Huan * Copyright 2014 Freescale Semiconductor, Inc. 3d60a2099SWang Huan * 4d60a2099SWang Huan * SPDX-License-Identifier: GPL-2.0+ 5d60a2099SWang Huan */ 6d60a2099SWang Huan 7d60a2099SWang Huan #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8d60a2099SWang Huan #define __ASM_ARCH_LS102XA_IMMAP_H_ 9d60a2099SWang Huan 10d60a2099SWang Huan #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11d60a2099SWang Huan #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12d60a2099SWang Huan #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13d60a2099SWang Huan #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14d60a2099SWang Huan 15d60a2099SWang Huan #define SOC_VER_SLS1020 0x00 16d60a2099SWang Huan #define SOC_VER_LS1020 0x10 17d60a2099SWang Huan #define SOC_VER_LS1021 0x11 18d60a2099SWang Huan #define SOC_VER_LS1022 0x12 19d60a2099SWang Huan 20036f3f33SAlison Wang #define SOC_MAJOR_VER_1_0 0x1 21036f3f33SAlison Wang #define SOC_MAJOR_VER_2_0 0x2 22036f3f33SAlison Wang 231a2826f6SXiubo Li #define CCSR_BRR_OFFSET 0xe4 241a2826f6SXiubo Li #define CCSR_SCRATCHRW1_OFFSET 0x200 251a2826f6SXiubo Li 26d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_SHIFT 25 27d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 28d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_SHIFT 16 29d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 30d60a2099SWang Huan 31d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_SHIFT 24 32d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 33d60a2099SWang Huan 34d60a2099SWang Huan #define TIMER_COMP_VAL 0xffffffff 35d60a2099SWang Huan #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 36d60a2099SWang Huan #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 37d60a2099SWang Huan 388ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 398ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 408ab967b6SAlison Wang 418ab967b6SAlison Wang #define DCFG_DCSR_PORCR1 0 428ab967b6SAlison Wang 4360d51736SAlison Wang /* 4460d51736SAlison Wang * Define default values for some CCSR macros to make header files cleaner 4560d51736SAlison Wang * 4660d51736SAlison Wang * To completely disable CCSR relocation in a board header file, define 4760d51736SAlison Wang * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 4860d51736SAlison Wang * to a value that is the same as CONFIG_SYS_CCSRBAR. 4960d51736SAlison Wang */ 5060d51736SAlison Wang 5160d51736SAlison Wang #ifdef CONFIG_SYS_CCSRBAR_PHYS 5260d51736SAlison Wang #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." 5360d51736SAlison Wang #endif 5460d51736SAlison Wang 5560d51736SAlison Wang #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 5660d51736SAlison Wang #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 5760d51736SAlison Wang #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 5860d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 5960d51736SAlison Wang #endif 6060d51736SAlison Wang 6160d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR 6260d51736SAlison Wang #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR 6360d51736SAlison Wang #endif 6460d51736SAlison Wang 6560d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 6660d51736SAlison Wang #ifdef CONFIG_PHYS_64BIT 6760d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 6860d51736SAlison Wang #else 6960d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 7060d51736SAlison Wang #endif 7160d51736SAlison Wang #endif 7260d51736SAlison Wang 7360d51736SAlison Wang #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 7460d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR 7560d51736SAlison Wang #endif 7660d51736SAlison Wang 7760d51736SAlison Wang #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 7860d51736SAlison Wang CONFIG_SYS_CCSRBAR_PHYS_LOW) 7960d51736SAlison Wang 80d60a2099SWang Huan struct sys_info { 81d60a2099SWang Huan unsigned long freq_processor[CONFIG_MAX_CPUS]; 82d60a2099SWang Huan unsigned long freq_systembus; 83d60a2099SWang Huan unsigned long freq_ddrbus; 84d60a2099SWang Huan unsigned long freq_localbus; 85d60a2099SWang Huan }; 86d60a2099SWang Huan 87d60a2099SWang Huan /* Device Configuration and Pin Control */ 88d60a2099SWang Huan struct ccsr_gur { 89d60a2099SWang Huan u32 porsr1; /* POR status 1 */ 90d60a2099SWang Huan u32 porsr2; /* POR status 2 */ 91d60a2099SWang Huan u8 res_008[0x20-0x8]; 92d60a2099SWang Huan u32 gpporcr1; /* General-purpose POR configuration */ 93d60a2099SWang Huan u32 gpporcr2; 94d60a2099SWang Huan u32 dcfg_fusesr; /* Fuse status register */ 95d60a2099SWang Huan u8 res_02c[0x70-0x2c]; 96d60a2099SWang Huan u32 devdisr; /* Device disable control */ 97d60a2099SWang Huan u32 devdisr2; /* Device disable control 2 */ 98d60a2099SWang Huan u32 devdisr3; /* Device disable control 3 */ 99d60a2099SWang Huan u32 devdisr4; /* Device disable control 4 */ 100d60a2099SWang Huan u32 devdisr5; /* Device disable control 5 */ 101d60a2099SWang Huan u8 res_084[0x94-0x84]; 102d60a2099SWang Huan u32 coredisru; /* uppper portion for support of 64 cores */ 103d60a2099SWang Huan u32 coredisrl; /* lower portion for support of 64 cores */ 104d60a2099SWang Huan u8 res_09c[0xa4-0x9c]; 105d60a2099SWang Huan u32 svr; /* System version */ 106d60a2099SWang Huan u8 res_0a8[0xb0-0xa8]; 107d60a2099SWang Huan u32 rstcr; /* Reset control */ 108d60a2099SWang Huan u32 rstrqpblsr; /* Reset request preboot loader status */ 109d60a2099SWang Huan u8 res_0b8[0xc0-0xb8]; 110d60a2099SWang Huan u32 rstrqmr1; /* Reset request mask */ 111d60a2099SWang Huan u8 res_0c4[0xc8-0xc4]; 112d60a2099SWang Huan u32 rstrqsr1; /* Reset request status */ 113d60a2099SWang Huan u8 res_0cc[0xd4-0xcc]; 114d60a2099SWang Huan u32 rstrqwdtmrl; /* Reset request WDT mask */ 115d60a2099SWang Huan u8 res_0d8[0xdc-0xd8]; 116d60a2099SWang Huan u32 rstrqwdtsrl; /* Reset request WDT status */ 117d60a2099SWang Huan u8 res_0e0[0xe4-0xe0]; 118d60a2099SWang Huan u32 brrl; /* Boot release */ 119d60a2099SWang Huan u8 res_0e8[0x100-0xe8]; 120d60a2099SWang Huan u32 rcwsr[16]; /* Reset control word status */ 121d60a2099SWang Huan u8 res_140[0x200-0x140]; 122d60a2099SWang Huan u32 scratchrw[4]; /* Scratch Read/Write */ 123d60a2099SWang Huan u8 res_210[0x300-0x210]; 124d60a2099SWang Huan u32 scratchw1r[4]; /* Scratch Read (Write once) */ 125d60a2099SWang Huan u8 res_310[0x400-0x310]; 126d60a2099SWang Huan u32 crstsr; 127d60a2099SWang Huan u8 res_404[0x550-0x404]; 128d60a2099SWang Huan u32 sataliodnr; 129d60a2099SWang Huan u8 res_554[0x604-0x554]; 130d60a2099SWang Huan u32 pamubypenr; 131d60a2099SWang Huan u32 dmacr1; 132d60a2099SWang Huan u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 133d60a2099SWang Huan u32 tp_ityp[64]; /* Topology Initiator Type Register */ 134d60a2099SWang Huan struct { 135d60a2099SWang Huan u32 upper; 136d60a2099SWang Huan u32 lower; 137d60a2099SWang Huan } tp_cluster[1]; /* Core Cluster n Topology Register */ 138d60a2099SWang Huan u8 res_848[0xe60-0x848]; 139d60a2099SWang Huan u32 ddrclkdr; 140d60a2099SWang Huan u8 res_e60[0xe68-0xe64]; 141d60a2099SWang Huan u32 ifcclkdr; 142d60a2099SWang Huan u8 res_e68[0xe80-0xe6c]; 143d60a2099SWang Huan u32 sdhcpcr; 144d60a2099SWang Huan }; 145d60a2099SWang Huan 146ebe4c1e6SClaudiu Manoil #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 1475757e06cShoria.geanta@freescale.com #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 148d60a2099SWang Huan #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 1490f5e5579SAlison Wang #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 1500f5e5579SAlison Wang #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 151d60a2099SWang Huan #define SCFG_PIXCLKCR_PXCKEN 0x80000000 152d612f0abSAlison Wang #define SCFG_QSPI_CLKSEL 0xc0100000 15388c857dfSAlison Wang #define SCFG_ENDIANCR_LE 0x80000000 154d60a2099SWang Huan 155d60a2099SWang Huan /* Supplemental Configuration Unit */ 156d60a2099SWang Huan struct ccsr_scfg { 157d60a2099SWang Huan u32 dpslpcr; 158d60a2099SWang Huan u32 resv0[2]; 159d60a2099SWang Huan u32 etsecclkdpslpcr; 160d60a2099SWang Huan u32 resv1[5]; 161d60a2099SWang Huan u32 fuseovrdcr; 162d60a2099SWang Huan u32 pixclkcr; 163d60a2099SWang Huan u32 resv2[5]; 164d60a2099SWang Huan u32 spimsicr; 165d60a2099SWang Huan u32 resv3[6]; 166d60a2099SWang Huan u32 pex1pmwrcr; 167d60a2099SWang Huan u32 pex1pmrdsr; 168d60a2099SWang Huan u32 resv4[3]; 169d60a2099SWang Huan u32 usb3prm1cr; 170d60a2099SWang Huan u32 usb4prm2cr; 171d60a2099SWang Huan u32 pex1rdmsgpldlsbsr; 172d60a2099SWang Huan u32 pex1rdmsgpldmsbsr; 173d60a2099SWang Huan u32 pex2rdmsgpldlsbsr; 174d60a2099SWang Huan u32 pex2rdmsgpldmsbsr; 175d60a2099SWang Huan u32 pex1rdmmsgrqsr; 176d60a2099SWang Huan u32 pex2rdmmsgrqsr; 177d60a2099SWang Huan u32 spimsiclrcr; 178ec245fd7SMinghuan Lian u32 pexmscportsr[2]; 179d60a2099SWang Huan u32 pex2pmwrcr; 180d60a2099SWang Huan u32 resv5[24]; 181d60a2099SWang Huan u32 mac1_streamid; 182d60a2099SWang Huan u32 mac2_streamid; 183d60a2099SWang Huan u32 mac3_streamid; 184d60a2099SWang Huan u32 pex1_streamid; 185d60a2099SWang Huan u32 pex2_streamid; 186d60a2099SWang Huan u32 dma_streamid; 187d60a2099SWang Huan u32 sata_streamid; 188d60a2099SWang Huan u32 usb3_streamid; 189d60a2099SWang Huan u32 qe_streamid; 190d60a2099SWang Huan u32 sdhc_streamid; 191d60a2099SWang Huan u32 adma_streamid; 192d60a2099SWang Huan u32 letechsftrstcr; 193d60a2099SWang Huan u32 core0_sft_rst; 194d60a2099SWang Huan u32 core1_sft_rst; 195d60a2099SWang Huan u32 resv6[1]; 196d60a2099SWang Huan u32 usb_hi_addr; 197d60a2099SWang Huan u32 etsecclkadjcr; 198d60a2099SWang Huan u32 sai_clk; 199d60a2099SWang Huan u32 resv7[1]; 200d60a2099SWang Huan u32 dcu_streamid; 201d60a2099SWang Huan u32 usb2_streamid; 202d60a2099SWang Huan u32 ftm_reset; 203d60a2099SWang Huan u32 altcbar; 204d60a2099SWang Huan u32 qspi_cfg; 205d60a2099SWang Huan u32 pmcintecr; 206d60a2099SWang Huan u32 pmcintlecr; 207d60a2099SWang Huan u32 pmcintsr; 208d60a2099SWang Huan u32 qos1; 209d60a2099SWang Huan u32 qos2; 210d60a2099SWang Huan u32 qos3; 211d60a2099SWang Huan u32 cci_cfg; 21288c857dfSAlison Wang u32 endiancr; 213d60a2099SWang Huan u32 etsecdmamcr; 214d60a2099SWang Huan u32 usb3prm3cr; 215d60a2099SWang Huan u32 resv9[1]; 216d60a2099SWang Huan u32 debug_streamid; 217d60a2099SWang Huan u32 resv10[5]; 218d60a2099SWang Huan u32 snpcnfgcr; 219d60a2099SWang Huan u32 resv11[1]; 220d60a2099SWang Huan u32 intpcr; 221d60a2099SWang Huan u32 resv12[20]; 222d60a2099SWang Huan u32 scfgrevcr; 223d60a2099SWang Huan u32 coresrencr; 224d60a2099SWang Huan u32 pex2pmrdsr; 225d60a2099SWang Huan u32 ddrc1cr; 226d60a2099SWang Huan u32 ddrc2cr; 227d60a2099SWang Huan u32 ddrc3cr; 228d60a2099SWang Huan u32 ddrc4cr; 229d60a2099SWang Huan u32 ddrgcr; 230d60a2099SWang Huan u32 resv13[120]; 231d60a2099SWang Huan u32 qeioclkcr; 232d60a2099SWang Huan u32 etsecmcr; 233d60a2099SWang Huan u32 sdhciovserlcr; 234d60a2099SWang Huan u32 resv14[61]; 235d8222dbeSTang Yuantian u32 sparecr[8]; 236d60a2099SWang Huan }; 237d60a2099SWang Huan 238d60a2099SWang Huan /* Clocking */ 239d60a2099SWang Huan struct ccsr_clk { 240d60a2099SWang Huan struct { 241d60a2099SWang Huan u32 clkcncsr; /* core cluster n clock control status */ 242d60a2099SWang Huan u8 res_004[0x1c]; 243d60a2099SWang Huan } clkcsr[2]; 244d60a2099SWang Huan u8 res_040[0x7c0]; /* 0x100 */ 245d60a2099SWang Huan struct { 246d60a2099SWang Huan u32 pllcngsr; 247d60a2099SWang Huan u8 res_804[0x1c]; 248d60a2099SWang Huan } pllcgsr[2]; 249d60a2099SWang Huan u8 res_840[0x1c0]; 250d60a2099SWang Huan u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 251d60a2099SWang Huan u8 res_a04[0x1fc]; 252d60a2099SWang Huan u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 253d60a2099SWang Huan u8 res_c04[0x1c]; 254d60a2099SWang Huan u32 plldgsr; /* 0xc20 DDR PLL General Status */ 255d60a2099SWang Huan u8 res_c24[0x3dc]; 256d60a2099SWang Huan }; 257d60a2099SWang Huan 258d60a2099SWang Huan /* System Counter */ 259d60a2099SWang Huan struct sctr_regs { 260d60a2099SWang Huan u32 cntcr; 261d60a2099SWang Huan u32 cntsr; 262d60a2099SWang Huan u32 cntcv1; 263d60a2099SWang Huan u32 cntcv2; 264d60a2099SWang Huan u32 resv1[4]; 265d60a2099SWang Huan u32 cntfid0; 266d60a2099SWang Huan u32 cntfid1; 267d60a2099SWang Huan u32 resv2[1002]; 268d60a2099SWang Huan u32 counterid[12]; 269d60a2099SWang Huan }; 270d60a2099SWang Huan 271d60a2099SWang Huan #define MAX_SERDES 1 272d60a2099SWang Huan #define SRDS_MAX_LANES 4 273d60a2099SWang Huan #define SRDS_MAX_BANK 2 274d60a2099SWang Huan 275d60a2099SWang Huan #define SRDS_RSTCTL_RST 0x80000000 276d60a2099SWang Huan #define SRDS_RSTCTL_RSTDONE 0x40000000 277d60a2099SWang Huan #define SRDS_RSTCTL_RSTERR 0x20000000 278d60a2099SWang Huan #define SRDS_RSTCTL_SWRST 0x10000000 279d60a2099SWang Huan #define SRDS_RSTCTL_SDEN 0x00000020 280d60a2099SWang Huan #define SRDS_RSTCTL_SDRST_B 0x00000040 281d60a2099SWang Huan #define SRDS_RSTCTL_PLLRST_B 0x00000080 282d60a2099SWang Huan #define SRDS_PLLCR0_POFF 0x80000000 283d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 284d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 285d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 286d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 287d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 288d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 289d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 290d60a2099SWang Huan #define SRDS_PLLCR0_PLL_LCK 0x00800000 291d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 292d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 293d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 294d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 295d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 296d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 297d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 298d60a2099SWang Huan #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 299d60a2099SWang Huan 300d60a2099SWang Huan struct ccsr_serdes { 301d60a2099SWang Huan struct { 302d60a2099SWang Huan u32 rstctl; /* Reset Control Register */ 303d60a2099SWang Huan 304d60a2099SWang Huan u32 pllcr0; /* PLL Control Register 0 */ 305d60a2099SWang Huan 306d60a2099SWang Huan u32 pllcr1; /* PLL Control Register 1 */ 307d60a2099SWang Huan u32 res_0c; /* 0x00c */ 308d60a2099SWang Huan u32 pllcr3; 309d60a2099SWang Huan u32 pllcr4; 310d60a2099SWang Huan u8 res_18[0x20-0x18]; 311d60a2099SWang Huan } bank[2]; 312d60a2099SWang Huan u8 res_40[0x90-0x40]; 313d60a2099SWang Huan u32 srdstcalcr; /* 0x90 TX Calibration Control */ 314d60a2099SWang Huan u8 res_94[0xa0-0x94]; 315d60a2099SWang Huan u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 316d60a2099SWang Huan u8 res_a4[0xb0-0xa4]; 317d60a2099SWang Huan u32 srdsgr0; /* 0xb0 General Register 0 */ 318d60a2099SWang Huan u8 res_b4[0xe0-0xb4]; 319d60a2099SWang Huan u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 320d60a2099SWang Huan u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 321d60a2099SWang Huan u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 322d60a2099SWang Huan u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 323d60a2099SWang Huan u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 324d60a2099SWang Huan u8 res_f4[0x100-0xf4]; 325d60a2099SWang Huan struct { 326d60a2099SWang Huan u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 327d60a2099SWang Huan u8 res_104[0x120-0x104]; 328d60a2099SWang Huan } srdslnpssr[4]; 329d60a2099SWang Huan u8 res_180[0x300-0x180]; 330d60a2099SWang Huan u32 srdspexeqcr; 331d60a2099SWang Huan u32 srdspexeqpcr[11]; 332d60a2099SWang Huan u8 res_330[0x400-0x330]; 333d60a2099SWang Huan u32 srdspexapcr; 334d60a2099SWang Huan u8 res_404[0x440-0x404]; 335d60a2099SWang Huan u32 srdspexbpcr; 336d60a2099SWang Huan u8 res_444[0x800-0x444]; 337d60a2099SWang Huan struct { 338d60a2099SWang Huan u32 gcr0; /* 0x800 General Control Register 0 */ 339d60a2099SWang Huan u32 gcr1; /* 0x804 General Control Register 1 */ 340d60a2099SWang Huan u32 gcr2; /* 0x808 General Control Register 2 */ 341d60a2099SWang Huan u32 sscr0; 342d60a2099SWang Huan u32 recr0; /* 0x810 Receive Equalization Control */ 343d60a2099SWang Huan u32 recr1; 344d60a2099SWang Huan u32 tecr0; /* 0x818 Transmit Equalization Control */ 345d60a2099SWang Huan u32 sscr1; 346d60a2099SWang Huan u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 347d60a2099SWang Huan u8 res_824[0x83c-0x824]; 348d60a2099SWang Huan u32 tcsr3; 349d60a2099SWang Huan } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 350d60a2099SWang Huan u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 351d60a2099SWang Huan }; 352d60a2099SWang Huan 353d60a2099SWang Huan #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 354d60a2099SWang Huan #define CCI400_CTRLORD_EN_BARRIER 0 355644bc7ecSJason Jin #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 3567df50fd3SAlison Wang #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 3577df50fd3SAlison Wang #define CCI400_SNOOP_REQ_EN 0x00000001 358d60a2099SWang Huan 359d60a2099SWang Huan /* CCI-400 registers */ 360d60a2099SWang Huan struct ccsr_cci400 { 361d60a2099SWang Huan u32 ctrl_ord; /* Control Override */ 362d60a2099SWang Huan u32 spec_ctrl; /* Speculation Control */ 363d60a2099SWang Huan u32 secure_access; /* Secure Access */ 364d60a2099SWang Huan u32 status; /* Status */ 365d60a2099SWang Huan u32 impr_err; /* Imprecise Error */ 366d60a2099SWang Huan u8 res_14[0x100 - 0x14]; 367d60a2099SWang Huan u32 pmcr; /* Performance Monitor Control */ 368d60a2099SWang Huan u8 res_104[0xfd0 - 0x104]; 369d60a2099SWang Huan u32 pid[8]; /* Peripheral ID */ 370d60a2099SWang Huan u32 cid[4]; /* Component ID */ 371d60a2099SWang Huan struct { 372d60a2099SWang Huan u32 snoop_ctrl; /* Snoop Control */ 373d60a2099SWang Huan u32 sha_ord; /* Shareable Override */ 374d60a2099SWang Huan u8 res_1008[0x1100 - 0x1008]; 375d60a2099SWang Huan u32 rc_qos_ord; /* read channel QoS Value Override */ 376d60a2099SWang Huan u32 wc_qos_ord; /* read channel QoS Value Override */ 377d60a2099SWang Huan u8 res_1108[0x110c - 0x1108]; 378d60a2099SWang Huan u32 qos_ctrl; /* QoS Control */ 379d60a2099SWang Huan u32 max_ot; /* Max OT */ 380d60a2099SWang Huan u8 res_1114[0x1130 - 0x1114]; 381d60a2099SWang Huan u32 target_lat; /* Target Latency */ 382d60a2099SWang Huan u32 latency_regu; /* Latency Regulation */ 383d60a2099SWang Huan u32 qos_range; /* QoS Range */ 384d60a2099SWang Huan u8 res_113c[0x2000 - 0x113c]; 385d60a2099SWang Huan } slave[5]; /* Slave Interface */ 386d60a2099SWang Huan u8 res_6000[0x9004 - 0x6000]; 387d60a2099SWang Huan u32 cycle_counter; /* Cycle counter */ 388d60a2099SWang Huan u32 count_ctrl; /* Count Control */ 389d60a2099SWang Huan u32 overflow_status; /* Overflow Flag Status */ 390d60a2099SWang Huan u8 res_9010[0xa000 - 0x9010]; 391d60a2099SWang Huan struct { 392d60a2099SWang Huan u32 event_select; /* Event Select */ 393d60a2099SWang Huan u32 event_count; /* Event Count */ 394d60a2099SWang Huan u32 counter_ctrl; /* Counter Control */ 395d60a2099SWang Huan u32 overflow_status; /* Overflow Flag Status */ 396d60a2099SWang Huan u8 res_a010[0xb000 - 0xa010]; 397d60a2099SWang Huan } pcounter[4]; /* Performance Counter */ 398d60a2099SWang Huan u8 res_e004[0x10000 - 0xe004]; 399d60a2099SWang Huan }; 400d09e401bSRamneek Mehresh 401*4632ad77Stang yuantian /* AHCI (sata) register map */ 402*4632ad77Stang yuantian struct ccsr_ahci { 403*4632ad77Stang yuantian u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 404*4632ad77Stang yuantian u32 pcfg; /* port config */ 405*4632ad77Stang yuantian u32 ppcfg; /* port phy1 config */ 406*4632ad77Stang yuantian u32 pp2c; /* port phy2 config */ 407*4632ad77Stang yuantian u32 pp3c; /* port phy3 config */ 408*4632ad77Stang yuantian u32 pp4c; /* port phy4 config */ 409*4632ad77Stang yuantian u32 pp5c; /* port phy5 config */ 410*4632ad77Stang yuantian u32 paxic; /* port AXI config */ 411*4632ad77Stang yuantian u32 axicc; /* AXI cache control */ 412*4632ad77Stang yuantian u32 axipc; /* AXI PROT control */ 413*4632ad77Stang yuantian u32 ptc; /* port Trans Config */ 414*4632ad77Stang yuantian u32 pts; /* port Trans Status */ 415*4632ad77Stang yuantian u32 plc; /* port link config */ 416*4632ad77Stang yuantian u32 plc1; /* port link config1 */ 417*4632ad77Stang yuantian u32 plc2; /* port link config2 */ 418*4632ad77Stang yuantian u32 pls; /* port link status */ 419*4632ad77Stang yuantian u32 pls1; /* port link status1 */ 420*4632ad77Stang yuantian u32 pcmdc; /* port CMD config */ 421*4632ad77Stang yuantian u32 ppcs; /* port phy control status */ 422*4632ad77Stang yuantian u32 pberr; /* port 0/1 BIST error */ 423*4632ad77Stang yuantian u32 cmds; /* port 0/1 CMD status error */ 424*4632ad77Stang yuantian }; 425d60a2099SWang Huan #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 426