1d60a2099SWang Huan /* 2d60a2099SWang Huan * Copyright 2014 Freescale Semiconductor, Inc. 3d60a2099SWang Huan * 4d60a2099SWang Huan * SPDX-License-Identifier: GPL-2.0+ 5d60a2099SWang Huan */ 6d60a2099SWang Huan 7d60a2099SWang Huan #ifndef __ASM_ARCH_LS102XA_IMMAP_H_ 8d60a2099SWang Huan #define __ASM_ARCH_LS102XA_IMMAP_H_ 9d60a2099SWang Huan 10d60a2099SWang Huan #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 11d60a2099SWang Huan #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 12d60a2099SWang Huan #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) 13d60a2099SWang Huan #define IS_E_PROCESSOR(svr) (svr & 0x80000) 14d60a2099SWang Huan 15d60a2099SWang Huan #define SOC_VER_SLS1020 0x00 16d60a2099SWang Huan #define SOC_VER_LS1020 0x10 17d60a2099SWang Huan #define SOC_VER_LS1021 0x11 18d60a2099SWang Huan #define SOC_VER_LS1022 0x12 19d60a2099SWang Huan 20*1a2826f6SXiubo Li #define CCSR_BRR_OFFSET 0xe4 21*1a2826f6SXiubo Li #define CCSR_SCRATCHRW1_OFFSET 0x200 22*1a2826f6SXiubo Li 23d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_SHIFT 25 24d60a2099SWang Huan #define RCWSR0_SYS_PLL_RAT_MASK 0x1f 25d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_SHIFT 16 26d60a2099SWang Huan #define RCWSR0_MEM_PLL_RAT_MASK 0x3f 27d60a2099SWang Huan 28d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_SHIFT 24 29d60a2099SWang Huan #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 30d60a2099SWang Huan 31d60a2099SWang Huan #define TIMER_COMP_VAL 0xffffffff 32d60a2099SWang Huan #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 33d60a2099SWang Huan #define SYS_COUNTER_CTRL_ENABLE (1 << 24) 34d60a2099SWang Huan 358ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 368ab967b6SAlison Wang #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 378ab967b6SAlison Wang 388ab967b6SAlison Wang #define DCFG_DCSR_PORCR1 0 398ab967b6SAlison Wang 40d60a2099SWang Huan struct sys_info { 41d60a2099SWang Huan unsigned long freq_processor[CONFIG_MAX_CPUS]; 42d60a2099SWang Huan unsigned long freq_systembus; 43d60a2099SWang Huan unsigned long freq_ddrbus; 44d60a2099SWang Huan unsigned long freq_localbus; 45d60a2099SWang Huan }; 46d60a2099SWang Huan 47d60a2099SWang Huan /* Device Configuration and Pin Control */ 48d60a2099SWang Huan struct ccsr_gur { 49d60a2099SWang Huan u32 porsr1; /* POR status 1 */ 50d60a2099SWang Huan u32 porsr2; /* POR status 2 */ 51d60a2099SWang Huan u8 res_008[0x20-0x8]; 52d60a2099SWang Huan u32 gpporcr1; /* General-purpose POR configuration */ 53d60a2099SWang Huan u32 gpporcr2; 54d60a2099SWang Huan u32 dcfg_fusesr; /* Fuse status register */ 55d60a2099SWang Huan u8 res_02c[0x70-0x2c]; 56d60a2099SWang Huan u32 devdisr; /* Device disable control */ 57d60a2099SWang Huan u32 devdisr2; /* Device disable control 2 */ 58d60a2099SWang Huan u32 devdisr3; /* Device disable control 3 */ 59d60a2099SWang Huan u32 devdisr4; /* Device disable control 4 */ 60d60a2099SWang Huan u32 devdisr5; /* Device disable control 5 */ 61d60a2099SWang Huan u8 res_084[0x94-0x84]; 62d60a2099SWang Huan u32 coredisru; /* uppper portion for support of 64 cores */ 63d60a2099SWang Huan u32 coredisrl; /* lower portion for support of 64 cores */ 64d60a2099SWang Huan u8 res_09c[0xa4-0x9c]; 65d60a2099SWang Huan u32 svr; /* System version */ 66d60a2099SWang Huan u8 res_0a8[0xb0-0xa8]; 67d60a2099SWang Huan u32 rstcr; /* Reset control */ 68d60a2099SWang Huan u32 rstrqpblsr; /* Reset request preboot loader status */ 69d60a2099SWang Huan u8 res_0b8[0xc0-0xb8]; 70d60a2099SWang Huan u32 rstrqmr1; /* Reset request mask */ 71d60a2099SWang Huan u8 res_0c4[0xc8-0xc4]; 72d60a2099SWang Huan u32 rstrqsr1; /* Reset request status */ 73d60a2099SWang Huan u8 res_0cc[0xd4-0xcc]; 74d60a2099SWang Huan u32 rstrqwdtmrl; /* Reset request WDT mask */ 75d60a2099SWang Huan u8 res_0d8[0xdc-0xd8]; 76d60a2099SWang Huan u32 rstrqwdtsrl; /* Reset request WDT status */ 77d60a2099SWang Huan u8 res_0e0[0xe4-0xe0]; 78d60a2099SWang Huan u32 brrl; /* Boot release */ 79d60a2099SWang Huan u8 res_0e8[0x100-0xe8]; 80d60a2099SWang Huan u32 rcwsr[16]; /* Reset control word status */ 81d60a2099SWang Huan u8 res_140[0x200-0x140]; 82d60a2099SWang Huan u32 scratchrw[4]; /* Scratch Read/Write */ 83d60a2099SWang Huan u8 res_210[0x300-0x210]; 84d60a2099SWang Huan u32 scratchw1r[4]; /* Scratch Read (Write once) */ 85d60a2099SWang Huan u8 res_310[0x400-0x310]; 86d60a2099SWang Huan u32 crstsr; 87d60a2099SWang Huan u8 res_404[0x550-0x404]; 88d60a2099SWang Huan u32 sataliodnr; 89d60a2099SWang Huan u8 res_554[0x604-0x554]; 90d60a2099SWang Huan u32 pamubypenr; 91d60a2099SWang Huan u32 dmacr1; 92d60a2099SWang Huan u8 res_60c[0x740-0x60c]; /* add more registers when needed */ 93d60a2099SWang Huan u32 tp_ityp[64]; /* Topology Initiator Type Register */ 94d60a2099SWang Huan struct { 95d60a2099SWang Huan u32 upper; 96d60a2099SWang Huan u32 lower; 97d60a2099SWang Huan } tp_cluster[1]; /* Core Cluster n Topology Register */ 98d60a2099SWang Huan u8 res_848[0xe60-0x848]; 99d60a2099SWang Huan u32 ddrclkdr; 100d60a2099SWang Huan u8 res_e60[0xe68-0xe64]; 101d60a2099SWang Huan u32 ifcclkdr; 102d60a2099SWang Huan u8 res_e68[0xe80-0xe6c]; 103d60a2099SWang Huan u32 sdhcpcr; 104d60a2099SWang Huan }; 105d60a2099SWang Huan 106d60a2099SWang Huan #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f 107d60a2099SWang Huan #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 108d60a2099SWang Huan #define SCFG_PIXCLKCR_PXCKEN 0x80000000 109d612f0abSAlison Wang #define SCFG_QSPI_CLKSEL 0xc0100000 110d60a2099SWang Huan 111d60a2099SWang Huan /* Supplemental Configuration Unit */ 112d60a2099SWang Huan struct ccsr_scfg { 113d60a2099SWang Huan u32 dpslpcr; 114d60a2099SWang Huan u32 resv0[2]; 115d60a2099SWang Huan u32 etsecclkdpslpcr; 116d60a2099SWang Huan u32 resv1[5]; 117d60a2099SWang Huan u32 fuseovrdcr; 118d60a2099SWang Huan u32 pixclkcr; 119d60a2099SWang Huan u32 resv2[5]; 120d60a2099SWang Huan u32 spimsicr; 121d60a2099SWang Huan u32 resv3[6]; 122d60a2099SWang Huan u32 pex1pmwrcr; 123d60a2099SWang Huan u32 pex1pmrdsr; 124d60a2099SWang Huan u32 resv4[3]; 125d60a2099SWang Huan u32 usb3prm1cr; 126d60a2099SWang Huan u32 usb4prm2cr; 127d60a2099SWang Huan u32 pex1rdmsgpldlsbsr; 128d60a2099SWang Huan u32 pex1rdmsgpldmsbsr; 129d60a2099SWang Huan u32 pex2rdmsgpldlsbsr; 130d60a2099SWang Huan u32 pex2rdmsgpldmsbsr; 131d60a2099SWang Huan u32 pex1rdmmsgrqsr; 132d60a2099SWang Huan u32 pex2rdmmsgrqsr; 133d60a2099SWang Huan u32 spimsiclrcr; 134d60a2099SWang Huan u32 pex1mscportsr; 135d60a2099SWang Huan u32 pex2mscportsr; 136d60a2099SWang Huan u32 pex2pmwrcr; 137d60a2099SWang Huan u32 resv5[24]; 138d60a2099SWang Huan u32 mac1_streamid; 139d60a2099SWang Huan u32 mac2_streamid; 140d60a2099SWang Huan u32 mac3_streamid; 141d60a2099SWang Huan u32 pex1_streamid; 142d60a2099SWang Huan u32 pex2_streamid; 143d60a2099SWang Huan u32 dma_streamid; 144d60a2099SWang Huan u32 sata_streamid; 145d60a2099SWang Huan u32 usb3_streamid; 146d60a2099SWang Huan u32 qe_streamid; 147d60a2099SWang Huan u32 sdhc_streamid; 148d60a2099SWang Huan u32 adma_streamid; 149d60a2099SWang Huan u32 letechsftrstcr; 150d60a2099SWang Huan u32 core0_sft_rst; 151d60a2099SWang Huan u32 core1_sft_rst; 152d60a2099SWang Huan u32 resv6[1]; 153d60a2099SWang Huan u32 usb_hi_addr; 154d60a2099SWang Huan u32 etsecclkadjcr; 155d60a2099SWang Huan u32 sai_clk; 156d60a2099SWang Huan u32 resv7[1]; 157d60a2099SWang Huan u32 dcu_streamid; 158d60a2099SWang Huan u32 usb2_streamid; 159d60a2099SWang Huan u32 ftm_reset; 160d60a2099SWang Huan u32 altcbar; 161d60a2099SWang Huan u32 qspi_cfg; 162d60a2099SWang Huan u32 pmcintecr; 163d60a2099SWang Huan u32 pmcintlecr; 164d60a2099SWang Huan u32 pmcintsr; 165d60a2099SWang Huan u32 qos1; 166d60a2099SWang Huan u32 qos2; 167d60a2099SWang Huan u32 qos3; 168d60a2099SWang Huan u32 cci_cfg; 169d60a2099SWang Huan u32 resv8[1]; 170d60a2099SWang Huan u32 etsecdmamcr; 171d60a2099SWang Huan u32 usb3prm3cr; 172d60a2099SWang Huan u32 resv9[1]; 173d60a2099SWang Huan u32 debug_streamid; 174d60a2099SWang Huan u32 resv10[5]; 175d60a2099SWang Huan u32 snpcnfgcr; 176d60a2099SWang Huan u32 resv11[1]; 177d60a2099SWang Huan u32 intpcr; 178d60a2099SWang Huan u32 resv12[20]; 179d60a2099SWang Huan u32 scfgrevcr; 180d60a2099SWang Huan u32 coresrencr; 181d60a2099SWang Huan u32 pex2pmrdsr; 182d60a2099SWang Huan u32 ddrc1cr; 183d60a2099SWang Huan u32 ddrc2cr; 184d60a2099SWang Huan u32 ddrc3cr; 185d60a2099SWang Huan u32 ddrc4cr; 186d60a2099SWang Huan u32 ddrgcr; 187d60a2099SWang Huan u32 resv13[120]; 188d60a2099SWang Huan u32 qeioclkcr; 189d60a2099SWang Huan u32 etsecmcr; 190d60a2099SWang Huan u32 sdhciovserlcr; 191d60a2099SWang Huan u32 resv14[61]; 192d8222dbeSTang Yuantian u32 sparecr[8]; 193d60a2099SWang Huan }; 194d60a2099SWang Huan 195d60a2099SWang Huan /* Clocking */ 196d60a2099SWang Huan struct ccsr_clk { 197d60a2099SWang Huan struct { 198d60a2099SWang Huan u32 clkcncsr; /* core cluster n clock control status */ 199d60a2099SWang Huan u8 res_004[0x1c]; 200d60a2099SWang Huan } clkcsr[2]; 201d60a2099SWang Huan u8 res_040[0x7c0]; /* 0x100 */ 202d60a2099SWang Huan struct { 203d60a2099SWang Huan u32 pllcngsr; 204d60a2099SWang Huan u8 res_804[0x1c]; 205d60a2099SWang Huan } pllcgsr[2]; 206d60a2099SWang Huan u8 res_840[0x1c0]; 207d60a2099SWang Huan u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 208d60a2099SWang Huan u8 res_a04[0x1fc]; 209d60a2099SWang Huan u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 210d60a2099SWang Huan u8 res_c04[0x1c]; 211d60a2099SWang Huan u32 plldgsr; /* 0xc20 DDR PLL General Status */ 212d60a2099SWang Huan u8 res_c24[0x3dc]; 213d60a2099SWang Huan }; 214d60a2099SWang Huan 215d60a2099SWang Huan /* System Counter */ 216d60a2099SWang Huan struct sctr_regs { 217d60a2099SWang Huan u32 cntcr; 218d60a2099SWang Huan u32 cntsr; 219d60a2099SWang Huan u32 cntcv1; 220d60a2099SWang Huan u32 cntcv2; 221d60a2099SWang Huan u32 resv1[4]; 222d60a2099SWang Huan u32 cntfid0; 223d60a2099SWang Huan u32 cntfid1; 224d60a2099SWang Huan u32 resv2[1002]; 225d60a2099SWang Huan u32 counterid[12]; 226d60a2099SWang Huan }; 227d60a2099SWang Huan 228d60a2099SWang Huan #define MAX_SERDES 1 229d60a2099SWang Huan #define SRDS_MAX_LANES 4 230d60a2099SWang Huan #define SRDS_MAX_BANK 2 231d60a2099SWang Huan 232d60a2099SWang Huan #define SRDS_RSTCTL_RST 0x80000000 233d60a2099SWang Huan #define SRDS_RSTCTL_RSTDONE 0x40000000 234d60a2099SWang Huan #define SRDS_RSTCTL_RSTERR 0x20000000 235d60a2099SWang Huan #define SRDS_RSTCTL_SWRST 0x10000000 236d60a2099SWang Huan #define SRDS_RSTCTL_SDEN 0x00000020 237d60a2099SWang Huan #define SRDS_RSTCTL_SDRST_B 0x00000040 238d60a2099SWang Huan #define SRDS_RSTCTL_PLLRST_B 0x00000080 239d60a2099SWang Huan #define SRDS_PLLCR0_POFF 0x80000000 240d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 241d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 242d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 243d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 244d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 245d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 246d60a2099SWang Huan #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 247d60a2099SWang Huan #define SRDS_PLLCR0_PLL_LCK 0x00800000 248d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 249d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 250d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 251d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 252d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 253d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 254d60a2099SWang Huan #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 255d60a2099SWang Huan #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 256d60a2099SWang Huan 257d60a2099SWang Huan struct ccsr_serdes { 258d60a2099SWang Huan struct { 259d60a2099SWang Huan u32 rstctl; /* Reset Control Register */ 260d60a2099SWang Huan 261d60a2099SWang Huan u32 pllcr0; /* PLL Control Register 0 */ 262d60a2099SWang Huan 263d60a2099SWang Huan u32 pllcr1; /* PLL Control Register 1 */ 264d60a2099SWang Huan u32 res_0c; /* 0x00c */ 265d60a2099SWang Huan u32 pllcr3; 266d60a2099SWang Huan u32 pllcr4; 267d60a2099SWang Huan u8 res_18[0x20-0x18]; 268d60a2099SWang Huan } bank[2]; 269d60a2099SWang Huan u8 res_40[0x90-0x40]; 270d60a2099SWang Huan u32 srdstcalcr; /* 0x90 TX Calibration Control */ 271d60a2099SWang Huan u8 res_94[0xa0-0x94]; 272d60a2099SWang Huan u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 273d60a2099SWang Huan u8 res_a4[0xb0-0xa4]; 274d60a2099SWang Huan u32 srdsgr0; /* 0xb0 General Register 0 */ 275d60a2099SWang Huan u8 res_b4[0xe0-0xb4]; 276d60a2099SWang Huan u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 277d60a2099SWang Huan u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 278d60a2099SWang Huan u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 279d60a2099SWang Huan u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 280d60a2099SWang Huan u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 281d60a2099SWang Huan u8 res_f4[0x100-0xf4]; 282d60a2099SWang Huan struct { 283d60a2099SWang Huan u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 284d60a2099SWang Huan u8 res_104[0x120-0x104]; 285d60a2099SWang Huan } srdslnpssr[4]; 286d60a2099SWang Huan u8 res_180[0x300-0x180]; 287d60a2099SWang Huan u32 srdspexeqcr; 288d60a2099SWang Huan u32 srdspexeqpcr[11]; 289d60a2099SWang Huan u8 res_330[0x400-0x330]; 290d60a2099SWang Huan u32 srdspexapcr; 291d60a2099SWang Huan u8 res_404[0x440-0x404]; 292d60a2099SWang Huan u32 srdspexbpcr; 293d60a2099SWang Huan u8 res_444[0x800-0x444]; 294d60a2099SWang Huan struct { 295d60a2099SWang Huan u32 gcr0; /* 0x800 General Control Register 0 */ 296d60a2099SWang Huan u32 gcr1; /* 0x804 General Control Register 1 */ 297d60a2099SWang Huan u32 gcr2; /* 0x808 General Control Register 2 */ 298d60a2099SWang Huan u32 sscr0; 299d60a2099SWang Huan u32 recr0; /* 0x810 Receive Equalization Control */ 300d60a2099SWang Huan u32 recr1; 301d60a2099SWang Huan u32 tecr0; /* 0x818 Transmit Equalization Control */ 302d60a2099SWang Huan u32 sscr1; 303d60a2099SWang Huan u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 304d60a2099SWang Huan u8 res_824[0x83c-0x824]; 305d60a2099SWang Huan u32 tcsr3; 306d60a2099SWang Huan } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 307d60a2099SWang Huan u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 308d60a2099SWang Huan }; 309d60a2099SWang Huan 310d60a2099SWang Huan #define DDR_SDRAM_CFG 0x470c0008 311d60a2099SWang Huan #define DDR_CS0_BNDS 0x008000bf 312d60a2099SWang Huan #define DDR_CS0_CONFIG 0x80014302 313d60a2099SWang Huan #define DDR_TIMING_CFG_0 0x50550004 314d60a2099SWang Huan #define DDR_TIMING_CFG_1 0xbcb38c56 315d60a2099SWang Huan #define DDR_TIMING_CFG_2 0x0040d120 316d60a2099SWang Huan #define DDR_TIMING_CFG_3 0x010e1000 317d60a2099SWang Huan #define DDR_TIMING_CFG_4 0x00000001 318d60a2099SWang Huan #define DDR_TIMING_CFG_5 0x03401400 319d60a2099SWang Huan #define DDR_SDRAM_CFG_2 0x00401010 320d60a2099SWang Huan #define DDR_SDRAM_MODE 0x00061c60 321d60a2099SWang Huan #define DDR_SDRAM_MODE_2 0x00180000 322d60a2099SWang Huan #define DDR_SDRAM_INTERVAL 0x18600618 323d60a2099SWang Huan #define DDR_DDR_WRLVL_CNTL 0x8655f605 324d60a2099SWang Huan #define DDR_DDR_WRLVL_CNTL_2 0x05060607 325d60a2099SWang Huan #define DDR_DDR_WRLVL_CNTL_3 0x05050505 326d60a2099SWang Huan #define DDR_DDR_CDR1 0x80040000 327d60a2099SWang Huan #define DDR_DDR_CDR2 0x00000001 328d60a2099SWang Huan #define DDR_SDRAM_CLK_CNTL 0x02000000 329d60a2099SWang Huan #define DDR_DDR_ZQ_CNTL 0x89080600 330d60a2099SWang Huan #define DDR_CS0_CONFIG_2 0 331d60a2099SWang Huan #define DDR_SDRAM_CFG_MEM_EN 0x80000000 332d60a2099SWang Huan 333d60a2099SWang Huan /* DDR memory controller registers */ 334d60a2099SWang Huan struct ccsr_ddr { 335d60a2099SWang Huan u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 336d60a2099SWang Huan u32 resv1[1]; 337d60a2099SWang Huan u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 338d60a2099SWang Huan u32 resv2[1]; 339d60a2099SWang Huan u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 340d60a2099SWang Huan u32 resv3[1]; 341d60a2099SWang Huan u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 342d60a2099SWang Huan u32 resv4[25]; 343d60a2099SWang Huan u32 cs0_config; /* Chip Select Configuration */ 344d60a2099SWang Huan u32 cs1_config; /* Chip Select Configuration */ 345d60a2099SWang Huan u32 cs2_config; /* Chip Select Configuration */ 346d60a2099SWang Huan u32 cs3_config; /* Chip Select Configuration */ 347d60a2099SWang Huan u32 resv5[12]; 348d60a2099SWang Huan u32 cs0_config_2; /* Chip Select Configuration 2 */ 349d60a2099SWang Huan u32 cs1_config_2; /* Chip Select Configuration 2 */ 350d60a2099SWang Huan u32 cs2_config_2; /* Chip Select Configuration 2 */ 351d60a2099SWang Huan u32 cs3_config_2; /* Chip Select Configuration 2 */ 352d60a2099SWang Huan u32 resv6[12]; 353d60a2099SWang Huan u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 354d60a2099SWang Huan u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 355d60a2099SWang Huan u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 356d60a2099SWang Huan u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 357d60a2099SWang Huan u32 sdram_cfg; /* SDRAM Control Configuration */ 358d60a2099SWang Huan u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 359d60a2099SWang Huan u32 sdram_mode; /* SDRAM Mode Configuration */ 360d60a2099SWang Huan u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 361d60a2099SWang Huan u32 sdram_md_cntl; /* SDRAM Mode Control */ 362d60a2099SWang Huan u32 sdram_interval; /* SDRAM Interval Configuration */ 363d60a2099SWang Huan u32 sdram_data_init; /* SDRAM Data initialization */ 364d60a2099SWang Huan u32 resv7[1]; 365d60a2099SWang Huan u32 sdram_clk_cntl; /* SDRAM Clock Control */ 366d60a2099SWang Huan u32 resv8[5]; 367d60a2099SWang Huan u32 init_addr; /* training init addr */ 368d60a2099SWang Huan u32 init_ext_addr; /* training init extended addr */ 369d60a2099SWang Huan u32 resv9[4]; 370d60a2099SWang Huan u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 371d60a2099SWang Huan u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 372d60a2099SWang Huan u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ 373d60a2099SWang Huan u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ 374d60a2099SWang Huan u32 ddr_zq_cntl; /* ZQ calibration control*/ 375d60a2099SWang Huan u32 ddr_wrlvl_cntl; /* write leveling control*/ 376d60a2099SWang Huan u32 resv10[1]; 377d60a2099SWang Huan u32 ddr_sr_cntr; /* self refresvh counter */ 378d60a2099SWang Huan u32 ddr_sdram_rcw_1; /* Control Words 1 */ 379d60a2099SWang Huan u32 ddr_sdram_rcw_2; /* Control Words 2 */ 380d60a2099SWang Huan u32 resv11[2]; 381d60a2099SWang Huan u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 382d60a2099SWang Huan u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 383d60a2099SWang Huan u32 resv12[2]; 384d60a2099SWang Huan u32 ddr_sdram_rcw_3; /* Control Words 3 */ 385d60a2099SWang Huan u32 ddr_sdram_rcw_4; /* Control Words 4 */ 386d60a2099SWang Huan u32 ddr_sdram_rcw_5; /* Control Words 5 */ 387d60a2099SWang Huan u32 ddr_sdram_rcw_6; /* Control Words 6 */ 388d60a2099SWang Huan u32 resv13[20]; 389d60a2099SWang Huan u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 390d60a2099SWang Huan u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 391d60a2099SWang Huan u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 392d60a2099SWang Huan u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 393d60a2099SWang Huan u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 394d60a2099SWang Huan u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 395d60a2099SWang Huan u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */ 396d60a2099SWang Huan u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */ 397d60a2099SWang Huan u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */ 398d60a2099SWang Huan u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */ 399d60a2099SWang Huan u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */ 400d60a2099SWang Huan u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */ 401d60a2099SWang Huan u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */ 402d60a2099SWang Huan u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */ 403d60a2099SWang Huan u32 resv14[4]; 404d60a2099SWang Huan u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */ 405d60a2099SWang Huan u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */ 406d60a2099SWang Huan u32 resv15[2]; 407d60a2099SWang Huan u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */ 408d60a2099SWang Huan u32 resv16[15]; 409d60a2099SWang Huan u32 deskew_cntl; /* SDRAM Deskew Control */ 410d60a2099SWang Huan u32 resv17[545]; 411d60a2099SWang Huan u32 ddr_dsr1; /* Debug Status 1 */ 412d60a2099SWang Huan u32 ddr_dsr2; /* Debug Status 2 */ 413d60a2099SWang Huan u32 ddr_cdr1; /* Control Driver 1 */ 414d60a2099SWang Huan u32 ddr_cdr2; /* Control Driver 2 */ 415d60a2099SWang Huan u32 resv18[50]; 416d60a2099SWang Huan u32 ip_rev1; /* IP Block Revision 1 */ 417d60a2099SWang Huan u32 ip_rev2; /* IP Block Revision 2 */ 418d60a2099SWang Huan u32 eor; /* Enhanced Optimization Register */ 419d60a2099SWang Huan u32 resv19[63]; 420d60a2099SWang Huan u32 mtcr; /* Memory Test Control Register */ 421d60a2099SWang Huan u32 resv20[7]; 422d60a2099SWang Huan u32 mtp1; /* Memory Test Pattern 1 */ 423d60a2099SWang Huan u32 mtp2; /* Memory Test Pattern 2 */ 424d60a2099SWang Huan u32 mtp3; /* Memory Test Pattern 3 */ 425d60a2099SWang Huan u32 mtp4; /* Memory Test Pattern 4 */ 426d60a2099SWang Huan u32 mtp5; /* Memory Test Pattern 5 */ 427d60a2099SWang Huan u32 mtp6; /* Memory Test Pattern 6 */ 428d60a2099SWang Huan u32 mtp7; /* Memory Test Pattern 7 */ 429d60a2099SWang Huan u32 mtp8; /* Memory Test Pattern 8 */ 430d60a2099SWang Huan u32 mtp9; /* Memory Test Pattern 9 */ 431d60a2099SWang Huan u32 mtp10; /* Memory Test Pattern 10 */ 432d60a2099SWang Huan u32 resv21[6]; 433d60a2099SWang Huan u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */ 434d60a2099SWang Huan u32 ddr_mt_st_addr; /* Memory Test Start Address */ 435d60a2099SWang Huan u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */ 436d60a2099SWang Huan u32 ddr_mt_end_addr; /* Memory Test End Address */ 437d60a2099SWang Huan u32 resv22[36]; 438d60a2099SWang Huan u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 439d60a2099SWang Huan u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 440d60a2099SWang Huan u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 441d60a2099SWang Huan u32 resv23[5]; 442d60a2099SWang Huan u32 capture_data_hi; /* Data Path Read Capture High */ 443d60a2099SWang Huan u32 capture_data_lo; /* Data Path Read Capture Low */ 444d60a2099SWang Huan u32 capture_ecc; /* Data Path Read Capture ECC */ 445d60a2099SWang Huan u32 resv24[5]; 446d60a2099SWang Huan u32 err_detect; /* Error Detect */ 447d60a2099SWang Huan u32 err_disable; /* Error Disable */ 448d60a2099SWang Huan u32 err_int_en; 449d60a2099SWang Huan u32 capture_attributes; /* Error Attrs Capture */ 450d60a2099SWang Huan u32 capture_address; /* Error Addr Capture */ 451d60a2099SWang Huan u32 capture_ext_address; /* Error Extended Addr Capture */ 452d60a2099SWang Huan u32 err_sbe; /* Single-Bit ECC Error Management */ 453d60a2099SWang Huan u32 resv25[105]; 454d60a2099SWang Huan }; 455d60a2099SWang Huan 456d60a2099SWang Huan #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 457d60a2099SWang Huan #define CCI400_CTRLORD_EN_BARRIER 0 458644bc7ecSJason Jin #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 459d60a2099SWang Huan 460d60a2099SWang Huan /* CCI-400 registers */ 461d60a2099SWang Huan struct ccsr_cci400 { 462d60a2099SWang Huan u32 ctrl_ord; /* Control Override */ 463d60a2099SWang Huan u32 spec_ctrl; /* Speculation Control */ 464d60a2099SWang Huan u32 secure_access; /* Secure Access */ 465d60a2099SWang Huan u32 status; /* Status */ 466d60a2099SWang Huan u32 impr_err; /* Imprecise Error */ 467d60a2099SWang Huan u8 res_14[0x100 - 0x14]; 468d60a2099SWang Huan u32 pmcr; /* Performance Monitor Control */ 469d60a2099SWang Huan u8 res_104[0xfd0 - 0x104]; 470d60a2099SWang Huan u32 pid[8]; /* Peripheral ID */ 471d60a2099SWang Huan u32 cid[4]; /* Component ID */ 472d60a2099SWang Huan struct { 473d60a2099SWang Huan u32 snoop_ctrl; /* Snoop Control */ 474d60a2099SWang Huan u32 sha_ord; /* Shareable Override */ 475d60a2099SWang Huan u8 res_1008[0x1100 - 0x1008]; 476d60a2099SWang Huan u32 rc_qos_ord; /* read channel QoS Value Override */ 477d60a2099SWang Huan u32 wc_qos_ord; /* read channel QoS Value Override */ 478d60a2099SWang Huan u8 res_1108[0x110c - 0x1108]; 479d60a2099SWang Huan u32 qos_ctrl; /* QoS Control */ 480d60a2099SWang Huan u32 max_ot; /* Max OT */ 481d60a2099SWang Huan u8 res_1114[0x1130 - 0x1114]; 482d60a2099SWang Huan u32 target_lat; /* Target Latency */ 483d60a2099SWang Huan u32 latency_regu; /* Latency Regulation */ 484d60a2099SWang Huan u32 qos_range; /* QoS Range */ 485d60a2099SWang Huan u8 res_113c[0x2000 - 0x113c]; 486d60a2099SWang Huan } slave[5]; /* Slave Interface */ 487d60a2099SWang Huan u8 res_6000[0x9004 - 0x6000]; 488d60a2099SWang Huan u32 cycle_counter; /* Cycle counter */ 489d60a2099SWang Huan u32 count_ctrl; /* Count Control */ 490d60a2099SWang Huan u32 overflow_status; /* Overflow Flag Status */ 491d60a2099SWang Huan u8 res_9010[0xa000 - 0x9010]; 492d60a2099SWang Huan struct { 493d60a2099SWang Huan u32 event_select; /* Event Select */ 494d60a2099SWang Huan u32 event_count; /* Event Count */ 495d60a2099SWang Huan u32 counter_ctrl; /* Counter Control */ 496d60a2099SWang Huan u32 overflow_status; /* Overflow Flag Status */ 497d60a2099SWang Huan u8 res_a010[0xb000 - 0xa010]; 498d60a2099SWang Huan } pcounter[4]; /* Performance Counter */ 499d60a2099SWang Huan u8 res_e004[0x10000 - 0xe004]; 500d60a2099SWang Huan }; 501d60a2099SWang Huan #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ 502