1 /*
2  * Copyright 2014, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
8 #define _ASM_ARMV7_LS102XA_CONFIG_
9 
10 #define CONFIG_SYS_CACHELINE_SIZE		64
11 
12 #define OCRAM_BASE_ADDR				0x10000000
13 #define OCRAM_SIZE				0x00020000
14 
15 #define CONFIG_SYS_IMMR				0x01000000
16 
17 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
22 #define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
23 #define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
24 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
25 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
26 #define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
27 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
28 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
29 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
30 
31 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
32 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
33 #define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
34 #define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
35 
36 #define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
37 #define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
38 
39 #define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
40 
41 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
42 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
43 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
44 
45 #define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
46 
47 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
48 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
49 
50 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
51 
52 #ifdef CONFIG_DDR_SPD
53 #define CONFIG_SYS_FSL_DDR_BE
54 #define CONFIG_VERY_BIG_RAM
55 #ifdef CONFIG_SYS_FSL_DDR4
56 #define CONFIG_SYS_FSL_DDRC_GEN4
57 #else
58 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3
59 #endif
60 #define CONFIG_SYS_FSL_DDR
61 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
62 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
63 #endif
64 
65 #define CONFIG_SYS_FSL_IFC_BE
66 #define CONFIG_SYS_FSL_ESDHC_BE
67 #define CONFIG_SYS_FSL_WDOG_BE
68 #define CONFIG_SYS_FSL_DSPI_BE
69 #define CONFIG_SYS_FSL_QSPI_BE
70 #define CONFIG_SYS_FSL_DCU_BE
71 #define CONFIG_SYS_FSL_SEC_LE
72 
73 #define DCU_LAYER_MAX_NUM			16
74 
75 #define CONFIG_SYS_FSL_SRDS_1
76 
77 #ifdef CONFIG_LS102XA
78 #define CONFIG_MAX_CPUS				2
79 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
80 #define CONFIG_NUM_DDR_CONTROLLERS		1
81 #define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
82 #define CONFIG_SYS_FSL_SEC_COMPAT		5
83 #else
84 #error SoC not defined
85 #endif
86 
87 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
88