1 /* 2 * Copyright 2014, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV7_LS102XA_CONFIG_ 8 #define _ASM_ARMV7_LS102XA_CONFIG_ 9 10 #define CONFIG_SYS_CACHELINE_SIZE 64 11 12 #define OCRAM_BASE_ADDR 0x10000000 13 #define OCRAM_SIZE 0x00020000 14 #define OCRAM_BASE_S_ADDR 0x10010000 15 #define OCRAM_S_SIZE 0x00010000 16 17 #define CONFIG_SYS_IMMR 0x01000000 18 #define CONFIG_SYS_DCSRBAR 0x20000000 19 20 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 21 22 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 23 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 24 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 25 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 26 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 27 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 28 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 29 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 30 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 31 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 32 #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 33 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 34 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 35 #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) 36 #define CONFIG_SYS_LS102XA_USB1_ADDR \ 37 (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) 38 39 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 40 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 41 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 42 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 43 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 44 45 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 46 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 47 48 #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 49 50 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 51 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 52 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 53 54 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 55 56 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 57 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 58 59 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 60 61 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 62 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 63 64 #ifdef CONFIG_DDR_SPD 65 #define CONFIG_SYS_FSL_DDR_BE 66 #define CONFIG_VERY_BIG_RAM 67 #ifdef CONFIG_SYS_FSL_DDR4 68 #define CONFIG_SYS_FSL_DDRC_GEN4 69 #else 70 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 71 #endif 72 #define CONFIG_SYS_FSL_DDR 73 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 74 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 75 #endif 76 77 #define CONFIG_SYS_FSL_IFC_BE 78 #define CONFIG_SYS_FSL_ESDHC_BE 79 #define CONFIG_SYS_FSL_WDOG_BE 80 #define CONFIG_SYS_FSL_DSPI_BE 81 #define CONFIG_SYS_FSL_QSPI_BE 82 #define CONFIG_SYS_FSL_DCU_BE 83 #define CONFIG_SYS_FSL_SEC_LE 84 85 #define DCU_LAYER_MAX_NUM 16 86 87 #define QE_MURAM_SIZE 0x6000UL 88 #define MAX_QE_RISC 1 89 #define QE_NUM_OF_SNUM 28 90 91 #define CONFIG_SYS_FSL_SRDS_1 92 93 #ifdef CONFIG_LS102XA 94 #define CONFIG_MAX_CPUS 2 95 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 98 #define CONFIG_SYS_FSL_SEC_COMPAT 5 99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 100 #else 101 #error SoC not defined 102 #endif 103 104 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 105