1 /* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef _LPC32XX_TIMER_H 21 #define _LPC32XX_TIMER_H 22 23 #include <asm/types.h> 24 25 /* Timer/Counter Registers */ 26 struct timer_regs { 27 u32 ir; /* Interrupt Register */ 28 u32 tcr; /* Timer Control Register */ 29 u32 tc; /* Timer Counter */ 30 u32 pr; /* Prescale Register */ 31 u32 pc; /* Prescale Counter */ 32 u32 mcr; /* Match Control Register */ 33 u32 mr[4]; /* Match Registers */ 34 u32 ccr; /* Capture Control Register */ 35 u32 cr[4]; /* Capture Registers */ 36 u32 emr; /* External Match Register */ 37 u32 reserved[12]; 38 u32 ctcr; /* Count Control Register */ 39 }; 40 41 /* Timer/Counter Interrupt Register bits */ 42 #define TIMER_IR_CR(n) (1 << ((n) + 4)) 43 #define TIMER_IR_MR(n) (1 << (n)) 44 45 /* Timer/Counter Timer Control Register bits */ 46 #define TIMER_TCR_COUNTER_RESET (1 << 1) 47 #define TIMER_TCR_COUNTER_ENABLE (1 << 0) 48 #define TIMER_TCR_COUNTER_DISABLE (0 << 0) 49 50 /* Timer/Counter Match Control Register bits */ 51 #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) 52 #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) 53 #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) 54 55 /* Timer/Counter Capture Control Register bits */ 56 #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) 57 #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) 58 #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) 59 60 /* Timer/Counter External Match Register bits */ 61 #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) 62 #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) 63 #define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) 64 #define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) 65 #define TIMER_EMR_EM(n) (1 << (n)) 66 67 /* Timer/Counter Count Control Register bits */ 68 #define TIMER_CTCR_INPUT(n) ((n) << 2) 69 #define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) 70 #define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) 71 #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) 72 #define TIMER_CTCR_MODE_TIMER (0x0 << 0) 73 74 #endif /* _LPC32XX_TIMER_H */ 75