1 /* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _LPC32XX_EMC_H 8 #define _LPC32XX_EMC_H 9 10 #include <asm/types.h> 11 12 /* EMC Registers */ 13 struct emc_regs { 14 u32 ctrl; /* Controls operation of the EMC */ 15 u32 status; /* Provides EMC status information */ 16 u32 config; /* Configures operation of the EMC */ 17 u32 reserved0[5]; 18 u32 control; /* Controls dyn memory operation */ 19 u32 refresh; /* Configures dyn memory refresh operation */ 20 u32 read_config; /* Configures the dyn memory read strategy */ 21 u32 reserved1; 22 u32 t_rp; /* Precharge command period */ 23 u32 t_ras; /* Active to precharge command period */ 24 u32 t_srex; /* Self-refresh exit time */ 25 u32 reserved2[2]; 26 u32 t_wr; /* Write recovery time */ 27 u32 t_rc; /* Active to active command period */ 28 u32 t_rfc; /* Auto-refresh period */ 29 u32 t_xsr; /* Exit self-refresh to active command time */ 30 u32 t_rrd; /* Active bank A to active bank B latency */ 31 u32 t_mrd; /* Load mode register to active command time */ 32 u32 t_cdlr; /* Last data in to read command time */ 33 u32 reserved3[8]; 34 u32 extended_wait; /* time for static memory rd/wr transfers */ 35 u32 reserved4[31]; 36 u32 config0; /* Configuration information for the SDRAM */ 37 u32 rascas0; /* RAS and CAS latencies for the SDRAM */ 38 u32 reserved5[6]; 39 u32 config1; /* Configuration information for the SDRAM */ 40 u32 rascas1; /* RAS and CAS latencies for the SDRAM */ 41 u32 reserved6[54]; 42 struct emc_stat_t { 43 u32 config; /* Static memory configuration */ 44 u32 waitwen; /* Delay from chip select to write enable */ 45 u32 waitoen; /* Delay to output enable */ 46 u32 waitrd; /* Delay to a read access */ 47 u32 waitpage; /* Delay for async page mode read */ 48 u32 waitwr; /* Delay to a write access */ 49 u32 waitturn; /* Number of bus turnaround cycles */ 50 u32 reserved; 51 } stat[4]; 52 u32 reserved7[96]; 53 struct emc_ahb_t { 54 u32 control; /* Control register for AHB */ 55 u32 status; /* Status register for AHB */ 56 u32 timeout; /* Timeout register for AHB */ 57 u32 reserved[5]; 58 } ahb[5]; 59 }; 60 61 /* Static Memory Configuration Register bits */ 62 #define EMC_STAT_CONFIG_WP (1 << 20) 63 #define EMC_STAT_CONFIG_EW (1 << 8) 64 #define EMC_STAT_CONFIG_PB (1 << 7) 65 #define EMC_STAT_CONFIG_PC (1 << 6) 66 #define EMC_STAT_CONFIG_PM (1 << 3) 67 #define EMC_STAT_CONFIG_32BIT (2 << 0) 68 #define EMC_STAT_CONFIG_16BIT (1 << 0) 69 #define EMC_STAT_CONFIG_8BIT (0 << 0) 70 71 /* Static Memory Delay Registers */ 72 #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) 73 #define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) 74 #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) 75 #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) 76 #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) 77 #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) 78 79 /* EMC settings for DRAM */ 80 struct emc_dram_settings { 81 u32 cmddelay; 82 u32 config0; 83 u32 rascas0; 84 u32 rdconfig; 85 u32 trp; 86 u32 tras; 87 u32 tsrex; 88 u32 twr; 89 u32 trc; 90 u32 trfc; 91 u32 txsr; 92 u32 trrd; 93 u32 tmrd; 94 u32 tcdlr; 95 u32 refresh; 96 u32 mode; 97 u32 emode; 98 }; 99 100 #endif /* _LPC32XX_EMC_H */ 101