1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 252f69f81SVladimir Zapolskiy /* 352f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 452f69f81SVladimir Zapolskiy */ 552f69f81SVladimir Zapolskiy 652f69f81SVladimir Zapolskiy #ifndef _LPC32XX_EMC_H 752f69f81SVladimir Zapolskiy #define _LPC32XX_EMC_H 852f69f81SVladimir Zapolskiy 952f69f81SVladimir Zapolskiy #include <asm/types.h> 1052f69f81SVladimir Zapolskiy 1152f69f81SVladimir Zapolskiy /* EMC Registers */ 1252f69f81SVladimir Zapolskiy struct emc_regs { 1352f69f81SVladimir Zapolskiy u32 ctrl; /* Controls operation of the EMC */ 1452f69f81SVladimir Zapolskiy u32 status; /* Provides EMC status information */ 1552f69f81SVladimir Zapolskiy u32 config; /* Configures operation of the EMC */ 1652f69f81SVladimir Zapolskiy u32 reserved0[5]; 1752f69f81SVladimir Zapolskiy u32 control; /* Controls dyn memory operation */ 1852f69f81SVladimir Zapolskiy u32 refresh; /* Configures dyn memory refresh operation */ 1952f69f81SVladimir Zapolskiy u32 read_config; /* Configures the dyn memory read strategy */ 2052f69f81SVladimir Zapolskiy u32 reserved1; 2152f69f81SVladimir Zapolskiy u32 t_rp; /* Precharge command period */ 2252f69f81SVladimir Zapolskiy u32 t_ras; /* Active to precharge command period */ 2352f69f81SVladimir Zapolskiy u32 t_srex; /* Self-refresh exit time */ 2452f69f81SVladimir Zapolskiy u32 reserved2[2]; 2552f69f81SVladimir Zapolskiy u32 t_wr; /* Write recovery time */ 2652f69f81SVladimir Zapolskiy u32 t_rc; /* Active to active command period */ 2752f69f81SVladimir Zapolskiy u32 t_rfc; /* Auto-refresh period */ 2852f69f81SVladimir Zapolskiy u32 t_xsr; /* Exit self-refresh to active command time */ 2952f69f81SVladimir Zapolskiy u32 t_rrd; /* Active bank A to active bank B latency */ 3052f69f81SVladimir Zapolskiy u32 t_mrd; /* Load mode register to active command time */ 3152f69f81SVladimir Zapolskiy u32 t_cdlr; /* Last data in to read command time */ 3252f69f81SVladimir Zapolskiy u32 reserved3[8]; 3352f69f81SVladimir Zapolskiy u32 extended_wait; /* time for static memory rd/wr transfers */ 3452f69f81SVladimir Zapolskiy u32 reserved4[31]; 3552f69f81SVladimir Zapolskiy u32 config0; /* Configuration information for the SDRAM */ 3652f69f81SVladimir Zapolskiy u32 rascas0; /* RAS and CAS latencies for the SDRAM */ 3752f69f81SVladimir Zapolskiy u32 reserved5[6]; 3852f69f81SVladimir Zapolskiy u32 config1; /* Configuration information for the SDRAM */ 3952f69f81SVladimir Zapolskiy u32 rascas1; /* RAS and CAS latencies for the SDRAM */ 4052f69f81SVladimir Zapolskiy u32 reserved6[54]; 4152f69f81SVladimir Zapolskiy struct emc_stat_t { 4252f69f81SVladimir Zapolskiy u32 config; /* Static memory configuration */ 4352f69f81SVladimir Zapolskiy u32 waitwen; /* Delay from chip select to write enable */ 4452f69f81SVladimir Zapolskiy u32 waitoen; /* Delay to output enable */ 4552f69f81SVladimir Zapolskiy u32 waitrd; /* Delay to a read access */ 4652f69f81SVladimir Zapolskiy u32 waitpage; /* Delay for async page mode read */ 4752f69f81SVladimir Zapolskiy u32 waitwr; /* Delay to a write access */ 4852f69f81SVladimir Zapolskiy u32 waitturn; /* Number of bus turnaround cycles */ 4952f69f81SVladimir Zapolskiy u32 reserved; 5052f69f81SVladimir Zapolskiy } stat[4]; 5152f69f81SVladimir Zapolskiy u32 reserved7[96]; 5252f69f81SVladimir Zapolskiy struct emc_ahb_t { 5352f69f81SVladimir Zapolskiy u32 control; /* Control register for AHB */ 5452f69f81SVladimir Zapolskiy u32 status; /* Status register for AHB */ 5552f69f81SVladimir Zapolskiy u32 timeout; /* Timeout register for AHB */ 5652f69f81SVladimir Zapolskiy u32 reserved[5]; 5752f69f81SVladimir Zapolskiy } ahb[5]; 5852f69f81SVladimir Zapolskiy }; 5952f69f81SVladimir Zapolskiy 6052f69f81SVladimir Zapolskiy /* Static Memory Configuration Register bits */ 6152f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_WP (1 << 20) 6252f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_EW (1 << 8) 6352f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PB (1 << 7) 6452f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PC (1 << 6) 6552f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PM (1 << 3) 6652f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_32BIT (2 << 0) 6752f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_16BIT (1 << 0) 6852f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_8BIT (0 << 0) 6952f69f81SVladimir Zapolskiy 7052f69f81SVladimir Zapolskiy /* Static Memory Delay Registers */ 7152f69f81SVladimir Zapolskiy #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) 72f0aa26f0SVladimir Zapolskiy #define EMC_STAT_WAITOEN(n) ((n) & 0x0F) 7352f69f81SVladimir Zapolskiy #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) 7452f69f81SVladimir Zapolskiy #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) 7552f69f81SVladimir Zapolskiy #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) 7652f69f81SVladimir Zapolskiy #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) 7752f69f81SVladimir Zapolskiy 78412ae53aSAlbert ARIBAUD \(3ADEV\) /* EMC settings for DRAM */ 79412ae53aSAlbert ARIBAUD \(3ADEV\) struct emc_dram_settings { 80412ae53aSAlbert ARIBAUD \(3ADEV\) u32 cmddelay; 81412ae53aSAlbert ARIBAUD \(3ADEV\) u32 config0; 82412ae53aSAlbert ARIBAUD \(3ADEV\) u32 rascas0; 83412ae53aSAlbert ARIBAUD \(3ADEV\) u32 rdconfig; 84412ae53aSAlbert ARIBAUD \(3ADEV\) u32 trp; 85412ae53aSAlbert ARIBAUD \(3ADEV\) u32 tras; 86412ae53aSAlbert ARIBAUD \(3ADEV\) u32 tsrex; 87412ae53aSAlbert ARIBAUD \(3ADEV\) u32 twr; 88412ae53aSAlbert ARIBAUD \(3ADEV\) u32 trc; 89412ae53aSAlbert ARIBAUD \(3ADEV\) u32 trfc; 90412ae53aSAlbert ARIBAUD \(3ADEV\) u32 txsr; 91412ae53aSAlbert ARIBAUD \(3ADEV\) u32 trrd; 92412ae53aSAlbert ARIBAUD \(3ADEV\) u32 tmrd; 93412ae53aSAlbert ARIBAUD \(3ADEV\) u32 tcdlr; 94412ae53aSAlbert ARIBAUD \(3ADEV\) u32 refresh; 95412ae53aSAlbert ARIBAUD \(3ADEV\) u32 mode; 96412ae53aSAlbert ARIBAUD \(3ADEV\) u32 emode; 97412ae53aSAlbert ARIBAUD \(3ADEV\) }; 98412ae53aSAlbert ARIBAUD \(3ADEV\) 9952f69f81SVladimir Zapolskiy #endif /* _LPC32XX_EMC_H */ 100