1*52f69f81SVladimir Zapolskiy /* 2*52f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*52f69f81SVladimir Zapolskiy * 4*52f69f81SVladimir Zapolskiy * This program is free software; you can redistribute it and/or 5*52f69f81SVladimir Zapolskiy * modify it under the terms of the GNU General Public License 6*52f69f81SVladimir Zapolskiy * as published by the Free Software Foundation; either version 2 7*52f69f81SVladimir Zapolskiy * of the License, or (at your option) any later version. 8*52f69f81SVladimir Zapolskiy * 9*52f69f81SVladimir Zapolskiy * This program is distributed in the hope that it will be useful, 10*52f69f81SVladimir Zapolskiy * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*52f69f81SVladimir Zapolskiy * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*52f69f81SVladimir Zapolskiy * GNU General Public License for more details. 13*52f69f81SVladimir Zapolskiy * 14*52f69f81SVladimir Zapolskiy * You should have received a copy of the GNU General Public License 15*52f69f81SVladimir Zapolskiy * along with this program; if not, write to the Free Software 16*52f69f81SVladimir Zapolskiy * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17*52f69f81SVladimir Zapolskiy * MA 02110-1301, USA. 18*52f69f81SVladimir Zapolskiy */ 19*52f69f81SVladimir Zapolskiy 20*52f69f81SVladimir Zapolskiy #ifndef _LPC32XX_EMC_H 21*52f69f81SVladimir Zapolskiy #define _LPC32XX_EMC_H 22*52f69f81SVladimir Zapolskiy 23*52f69f81SVladimir Zapolskiy #include <asm/types.h> 24*52f69f81SVladimir Zapolskiy 25*52f69f81SVladimir Zapolskiy /* EMC Registers */ 26*52f69f81SVladimir Zapolskiy struct emc_regs { 27*52f69f81SVladimir Zapolskiy u32 ctrl; /* Controls operation of the EMC */ 28*52f69f81SVladimir Zapolskiy u32 status; /* Provides EMC status information */ 29*52f69f81SVladimir Zapolskiy u32 config; /* Configures operation of the EMC */ 30*52f69f81SVladimir Zapolskiy u32 reserved0[5]; 31*52f69f81SVladimir Zapolskiy u32 control; /* Controls dyn memory operation */ 32*52f69f81SVladimir Zapolskiy u32 refresh; /* Configures dyn memory refresh operation */ 33*52f69f81SVladimir Zapolskiy u32 read_config; /* Configures the dyn memory read strategy */ 34*52f69f81SVladimir Zapolskiy u32 reserved1; 35*52f69f81SVladimir Zapolskiy u32 t_rp; /* Precharge command period */ 36*52f69f81SVladimir Zapolskiy u32 t_ras; /* Active to precharge command period */ 37*52f69f81SVladimir Zapolskiy u32 t_srex; /* Self-refresh exit time */ 38*52f69f81SVladimir Zapolskiy u32 reserved2[2]; 39*52f69f81SVladimir Zapolskiy u32 t_wr; /* Write recovery time */ 40*52f69f81SVladimir Zapolskiy u32 t_rc; /* Active to active command period */ 41*52f69f81SVladimir Zapolskiy u32 t_rfc; /* Auto-refresh period */ 42*52f69f81SVladimir Zapolskiy u32 t_xsr; /* Exit self-refresh to active command time */ 43*52f69f81SVladimir Zapolskiy u32 t_rrd; /* Active bank A to active bank B latency */ 44*52f69f81SVladimir Zapolskiy u32 t_mrd; /* Load mode register to active command time */ 45*52f69f81SVladimir Zapolskiy u32 t_cdlr; /* Last data in to read command time */ 46*52f69f81SVladimir Zapolskiy u32 reserved3[8]; 47*52f69f81SVladimir Zapolskiy u32 extended_wait; /* time for static memory rd/wr transfers */ 48*52f69f81SVladimir Zapolskiy u32 reserved4[31]; 49*52f69f81SVladimir Zapolskiy u32 config0; /* Configuration information for the SDRAM */ 50*52f69f81SVladimir Zapolskiy u32 rascas0; /* RAS and CAS latencies for the SDRAM */ 51*52f69f81SVladimir Zapolskiy u32 reserved5[6]; 52*52f69f81SVladimir Zapolskiy u32 config1; /* Configuration information for the SDRAM */ 53*52f69f81SVladimir Zapolskiy u32 rascas1; /* RAS and CAS latencies for the SDRAM */ 54*52f69f81SVladimir Zapolskiy u32 reserved6[54]; 55*52f69f81SVladimir Zapolskiy struct emc_stat_t { 56*52f69f81SVladimir Zapolskiy u32 config; /* Static memory configuration */ 57*52f69f81SVladimir Zapolskiy u32 waitwen; /* Delay from chip select to write enable */ 58*52f69f81SVladimir Zapolskiy u32 waitoen; /* Delay to output enable */ 59*52f69f81SVladimir Zapolskiy u32 waitrd; /* Delay to a read access */ 60*52f69f81SVladimir Zapolskiy u32 waitpage; /* Delay for async page mode read */ 61*52f69f81SVladimir Zapolskiy u32 waitwr; /* Delay to a write access */ 62*52f69f81SVladimir Zapolskiy u32 waitturn; /* Number of bus turnaround cycles */ 63*52f69f81SVladimir Zapolskiy u32 reserved; 64*52f69f81SVladimir Zapolskiy } stat[4]; 65*52f69f81SVladimir Zapolskiy u32 reserved7[96]; 66*52f69f81SVladimir Zapolskiy struct emc_ahb_t { 67*52f69f81SVladimir Zapolskiy u32 control; /* Control register for AHB */ 68*52f69f81SVladimir Zapolskiy u32 status; /* Status register for AHB */ 69*52f69f81SVladimir Zapolskiy u32 timeout; /* Timeout register for AHB */ 70*52f69f81SVladimir Zapolskiy u32 reserved[5]; 71*52f69f81SVladimir Zapolskiy } ahb[5]; 72*52f69f81SVladimir Zapolskiy }; 73*52f69f81SVladimir Zapolskiy 74*52f69f81SVladimir Zapolskiy /* Static Memory Configuration Register bits */ 75*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_WP (1 << 20) 76*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_EW (1 << 8) 77*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PB (1 << 7) 78*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PC (1 << 6) 79*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_PM (1 << 3) 80*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_32BIT (2 << 0) 81*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_16BIT (1 << 0) 82*52f69f81SVladimir Zapolskiy #define EMC_STAT_CONFIG_8BIT (0 << 0) 83*52f69f81SVladimir Zapolskiy 84*52f69f81SVladimir Zapolskiy /* Static Memory Delay Registers */ 85*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) 86*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) 87*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) 88*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) 89*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) 90*52f69f81SVladimir Zapolskiy #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) 91*52f69f81SVladimir Zapolskiy 92*52f69f81SVladimir Zapolskiy #endif /* _LPC32XX_EMC_H */ 93