1 /*
2  * LPC32xx DMA Controller Interface
3  *
4  * Copyright (C) 2008 by NXP Semiconductors
5  * @Author: Kevin Wells
6  * @Descr: Definitions for LPC3250 chip
7  * @References: NXP LPC3250 User's Guide
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef _LPC32XX_DMA_H
13 #define _LPC32XX_DMA_H
14 
15 #include <common.h>
16 
17 /*
18  * DMA linked list structure used with a channel's LLI register;
19  * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
20  * tables 84, 85, 86 & 87 for details.
21  */
22 struct lpc32xx_dmac_ll {
23 	u32 dma_src;
24 	u32 dma_dest;
25 	u32 next_lli;
26 	u32 next_ctrl;
27 };
28 
29 /* control register definitions */
30 #define DMAC_CHAN_INT_TC_EN	(1 << 31) /* channel terminal count interrupt */
31 #define DMAC_CHAN_DEST_AUTOINC	(1 << 27) /* automatic destination increment */
32 #define DMAC_CHAN_SRC_AUTOINC	(1 << 26) /* automatic source increment */
33 #define DMAC_CHAN_DEST_AHB1	(1 << 25) /* AHB1 master for dest. transfer */
34 #define DMAC_CHAN_DEST_WIDTH_32	(1 << 22) /* Destination data width selection */
35 #define DMAC_CHAN_SRC_WIDTH_32	(1 << 19) /* Source data width selection */
36 #define DMAC_CHAN_DEST_BURST_1	0
37 #define DMAC_CHAN_DEST_BURST_4	(1 << 15) /* Destination data burst size */
38 #define DMAC_CHAN_SRC_BURST_1	0
39 #define DMAC_CHAN_SRC_BURST_4	(1 << 12) /* Source data burst size */
40 
41 /*
42  * config_ch register definitions
43  * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
44  * DMAC_DEST_PERIP: Macro for loading destination peripheral
45  * DMAC_SRC_PERIP: Macro for loading source peripheral
46  */
47 #define DMAC_CHAN_FLOW_D_M2P	(0x1 << 11)
48 #define DMAC_CHAN_FLOW_D_P2M	(0x2 << 11)
49 #define DMAC_DEST_PERIP(n)	(((n) & 0x1F) << 6)
50 #define DMAC_SRC_PERIP(n)	(((n) & 0x1F) << 1)
51 
52 /*
53  * config_ch register definitions
54  * (source and destination peripheral ID numbers).
55  * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.
56  */
57 #define DMA_PERID_NAND1		1
58 
59 /* Channel enable bit */
60 #define DMAC_CHAN_ENABLE	(1 << 0)
61 
62 int lpc32xx_dma_get_channel(void);
63 int lpc32xx_dma_start_xfer(unsigned int channel,
64 			   const struct lpc32xx_dmac_ll *desc, u32 config);
65 int lpc32xx_dma_wait_status(unsigned int channel);
66 
67 #endif /* _LPC32XX_DMA_H */
68